// SPDX-License-Identifier: (GPL-2.0-or-later)
/*
 * Copyright (C) 2014 PHYTEC Messtechnik GmbH
 * Author: Christian Hemp <c.hemp@phytec.de>
 */

#include <dt-bindings/gpio/gpio.h>

/ {
	chosen {
		environment-nand {
			compatible = "barebox,environment";
			device-path = &environment_nand;
			status = "disabled";
		};

		environment-sd3 {
			compatible = "barebox,environment";
			device-path = &environment_usdhc3;
			status = "disabled";
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "mii";
	status = "disabled";
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	status = "okay";

	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "barebox";
			reg = <0x0 0x1000000>;
		};

		environment_nand: partition@400000 {
			label = "barebox-environment";
			reg = <0x1000000 0x100000>;
		};

		partition@420000 {
			label = "root";
			reg = <0x1100000 0x0>;
		};
	};
};

&i2c1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;

	eeprom: m24c32@50 {
		compatible = "st,24c32", "at24";
		reg = <0x50>;
		status = "disabled";
	};
};

&iomuxc {
	pinctrl-names = "default";

	pinctrl_enet: enetgrp {
		fsl,pins = <
			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
			MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3	0x1b0b0
			MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3	0x1b0b0
			MX6QDL_PAD_KEY_ROW1__ENET_COL		0x1b0b0
			MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2	0x1b0b0
			MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2	0x1b0b0
			MX6QDL_PAD_KEY_COL3__ENET_CRS		0x1b0b0
			MX6QDL_PAD_GPIO_18__ENET_RX_CLK		0x1b0b0
			MX6QDL_PAD_GPIO_19__ENET_TX_ER		0x1b0b0
		>;
	};

	pinctrl_gpmi_nand: gpmigrp {
		fsl,pins = <
			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
			MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
			MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
			MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22	0x80000000 /* CD */
		>;
	};
};

&ocotp {
	barebox,provide-mac-address = <&fec 0x620>;
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "disabled";
};

&usdhc3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc3>;
        cd-gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
        status = "disabled";

	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "barebox";
			reg = <0x0 0xe0000>;
		};

		environment_usdhc3: partition@e0000 {
			label = "barebox-environment";
			reg = <0xe0000 0x20000>;
		};
	};
};