/* * Copyright (C) 2015 PHYTEC America, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ / { model = "Phytec i.MX7 phyBOARD-Zeta"; compatible = "phytec,imx7d-pba-c-09", "phytec,imx7d-phycore-som", "fsl,imx7d"; regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; reg_usb_otg1_vbus: regulator@0 { compatible = "regulator-fixed"; reg = <0>; regulator-name = "usb_otg1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_usb_otg2_vbus: regulator@1 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "usb_otg2_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; enable-active-high; }; /* Enable if R9 is populated. Conflicts with userbtn2 on PEB-EVAL-02 */ /* reg_can1_3v3: regulator@2 { compatible = "regulator-fixed"; reg = <2>; regulator-name = "can1-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; enable-active-high; }; */ }; }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_2 &pinctrl_hog_lcd>; pinctrl_hog_2: hoggrp-2 { fsl,pins = < MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* SD1 CD */ MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* PCIe Disable */ MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x59 /* PCIe Reset */ MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* USB2 pwr */ MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 /* ETH2 Int_N */ MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x59 /* ETH2 Reset_n */ MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x59 /* User Button */ MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x39 /* Boot Circuit Buffer Enable 5K pull-up */ >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 >; }; pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59 MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59 >; }; pinctrl_enet2: enet2grp { fsl,pins = < MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5 >; }; }; &iomuxc_lpsr { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_lpsr_1 &pinctrl_hog_lpsr_lcd>; pinctrl_hog_lpsr_1: hoggrp-lpsr_1 { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 /* USB1 pwr */ >; }; pinctrl_uart5: uart5grp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x79 MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x79 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 >; }; }; &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; status = "disabled"; }; &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; no-1-8-v; /* Fixed voltage supply, doesn't support vsel */ enable-sdio-wakeup; keep-power-in-suspend; status = "disabled"; }; &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; /* Enable the following if SD1_RESET_B is used to enable/disable CAN xceiver * xceiver-supply = <®_can1_3v3>; */ status = "disabled"; }; &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, <&clks IMX7D_ENET2_TIME_ROOT_CLK>; assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; assigned-clock-rates = <0>, <100000000>; phy-mode = "rgmii"; phy-handle = <ðphy1>; fsl,magic-packet; phy-reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; status = "disabled"; }; /* same MDIO bus as PHY on phyCORE SOM */ &mdio { ethphy1: ethernet-phy@2 { compatible = "ethernet-phy-ieee802.3-c22"; interrupt-parent = <&gpio1>; interrupts = <9 0>; reg = <2>; rxdv-skew-ps = <0>; txen-skew-ps = <0>; rxd0-skew-ps = <0>; rxd1-skew-ps = <0>; rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; rxc-skew-ps = <1860>; txc-skew-ps = <1860>; }; }; &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; dr_mode = "host"; status = "disabled"; }; &usbotg2 { vbus-supply = <®_usb_otg2_vbus>; status = "disabled"; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,wdog_b; }; /* DTS pinmuxing and bindings for LCD adapter PEB-AV-02 */ &iomuxc { pinctrl_hog_lcd: hog_lcdgrp { fsl,pins = < MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79 >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f >; }; pinctrl_edt_ts_irq: tsirqgrp { fsl,pins = < MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 >; }; }; &iomuxc_lpsr { pinctrl_pwm3: pwmgrp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x30 >; }; pinctrl_hog_lpsr_lcd: hoggrp_lpsr_lcd { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x59 >; }; }; &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "disabled"; ft5406: ft5406@38 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_edt_ts_irq>; interrupt-parent = <&gpio2>; interrupts = <14 0>; reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; status = "disabled"; }; }; #include "imx7d-peb-av-02.dtsi" &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "disabled"; }; &backlight { pwms = <&pwm3 0 5000000>; enable-gpios = <&gpio1 1 0>; status = "disabled"; };