/* * Copyright (C) 2015 PHYTEC America, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include #include / { model = "Phytec i.MX7D phyCORE"; compatible = "phytec,imx7d-phycore-som", "fsl,imx7d"; memory { reg = <0x80000000 0x80000000>; }; }; &cpu0 { arm-supply = <&sw1a_reg>; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; regulators { sw1a_reg: sw1a { regulator-min-microvolt = <700000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <6250>; }; /* use sw1c_reg to align with pfuze100/pfuze200 */ sw1c_reg: sw1b { regulator-min-microvolt = <700000>; regulator-max-microvolt = <1475000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <6250>; }; sw2_reg: sw2 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1850000>; regulator-boot-on; regulator-always-on; }; sw3a_reg: sw3 { regulator-min-microvolt = <900000>; regulator-max-microvolt = <1650000>; regulator-boot-on; regulator-always-on; }; swbst_reg: swbst { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5150000>; }; snvs_reg: vsnvs { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <3000000>; regulator-boot-on; regulator-always-on; }; vref_reg: vrefddr { regulator-boot-on; regulator-always-on; }; vgen1_reg: vldo1 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; vgen2_reg: vldo2 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <1550000>; regulator-always-on; }; vgen3_reg: vccsd { regulator-min-microvolt = <2850000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; vgen4_reg: v33 { regulator-min-microvolt = <2850000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; vgen5_reg: vldo3 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; vgen6_reg: vldo4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; i2c_eeprom: eeprom@50 { compatible = "atmel,24c32"; pagesize = <32>; reg = <0x50>; status = "disabled"; }; i2c_rtc: rtc@68 { compatible = "mc,rv4162"; reg=<0x68>; status = "disabled"; }; }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_1>; pinctrl_hog_1: hoggrp-1 { fsl,pins = < MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* PMIC VSELECT */ MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* ENET1_RESET_B */ MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 /* ENET1_INT_B */ >; }; pinctrl_enet1: enet1grp { fsl,pins = < MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5d MX7D_PAD_SD3_CLK__SD3_CLK 0x1d MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d >; }; pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5e MX7D_PAD_SD3_CLK__SD3_CLK 0x1e MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e >; }; pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x5f MX7D_PAD_SD3_CLK__SD3_CLK 0x1f MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f >; }; pinctrl_qspi1_1: qspi1grp_1 { fsl,pins = < MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 >; }; }; &sdma { status = "okay"; }; &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, <&clks IMX7D_ENET1_TIME_ROOT_CLK>; assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; assigned-clock-rates = <0>, <100000000>; phy-mode = "rgmii"; phy-handle = <ðphy0>; fsl,magic-packet; phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; status = "disabled"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; /*ETH1 PHY on SOM, 25MHz crystal */ ethphy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; interrupt-parent = <&gpio2>; interrupts = <29 0>; reg = <1>; }; }; }; &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; assigned-clock-rates = <400000000>; bus-width = <8>; tuning-step = <2>; non-removable; status = "disabled"; };