// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Protonic Holland
 * Copyright 2019 NXP
 */

/dts-v1/;

#include <arm64/freescale/imx8mm.dtsi>
#include "imx8mm.dtsi"

/ {
	model = "Protonic PRT8MM";
	compatible = "prt,prt8mm", "fsl,imx8mm";

	chosen {
		stdout-path = &uart4;

		environment-sd {
			compatible = "barebox,environment";
			device-path = &part_env_sd;
			status = "disabled";
		};
		environment-emmc {
			compatible = "barebox,environment";
			device-path = &part_env_emmc;
			status = "disabled";
		};
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1>;
	dr_mode = "host";
	power-active-high;
	over-current-active-low;
	status = "okay";
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
	assigned-clock-rates = <100000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
		label = "barebox";
		reg = <0x0 0xe0000>;
	};

	part_env_sd: partition@e0000 {
		label = "barebox-environment";
		reg = <0xe0000 0x20000>;
	};
};

&usdhc3 {
	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	no-sdio;
	no-sd;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <1>;

	part_env_emmc: partition@e0000 {
		label = "barebox-environment";
		reg = <0xe0000 0x20000>;
	};
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400000c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400000c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400000c3
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400000c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400000c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400000c3
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x040
			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x040
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2grpgpio {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x0d4
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
		>;
	};

	pinctrl_usbotg1: usbotg1grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR		0x000
			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x000
		>;
	};
};