// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 * Copyright 2020-2021 Variscite Ltd.
 */

/dts-v1/;

#include <dt-bindings/usb/pd.h>
#include <arm64/freescale/imx8mp.dtsi>
#include "imx8mp.dtsi"

/ {
	compatible = "variscite,imx8mp-var-dart", "fsl,imx8mp";

	aliases {
		ethernet0 = &eqos;
		ethernet1 = &fec;
	};

	reg_eqos_phy: regulator-eqos-phy {
		compatible = "regulator-fixed";
		regulator-name = "eqos-phy";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-enable-ramp-delay = <20000>;
		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
	};

	reg_audio: regulator-audio-vdd {
		compatible = "regulator-fixed";
		regulator-name = "wm8904_supply";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};
};

&A53_0 {
	cpu-supply = <&buck2>;
};

&A53_1 {
	cpu-supply = <&buck2>;
};

&A53_2 {
	cpu-supply = <&buck2>;
};

&A53_3 {
	cpu-supply = <&buck2>;
};

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			at803x,eee-disabled;
			eee-broken-1000t;
			reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			reset-deassert-us = <20000>;
			vddio-supply = <&vddio0>;

			vddio0: vddio-regulator {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};
		};
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
	status = "okay";

	pca9450@25 {
		reg = <0x25>;
		compatible = "nxp,pca9450c";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio1>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			#address-cells = <1>;
			#size-cells = <0>;

			buck1: BUCK1 {
				regulator-name = "BUCK1";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck2: BUCK2 {
				regulator-name = "BUCK2";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
				nxp,dvs-run-voltage = <950000>;
				nxp,dvs-standby-voltage = <850000>;
			};

			buck4: BUCK4 {
				regulator-name = "BUCK4";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5: BUCK5 {
				regulator-name = "BUCK5";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6: BUCK6 {
				regulator-name = "BUCK6";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1: LDO1 {
				regulator-name = "LDO1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2: LDO2 {
				regulator-name = "LDO2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1150000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3: LDO3 {
				regulator-name = "LDO3";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4: LDO4 {
				regulator-name = "LDO4";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			ldo5: LDO5 {
				regulator-name = "LDO5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};
};

/* WIFI */
&usdhc1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
	bus-width = <4>;
	non-removable;
	keep-power-in-suspend;
	status = "okay";

	brcmf: bcrmf@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
	};
};

/* eMMC */
&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&snvs_pwrkey {
	status = "okay";
};

&iomuxc {
	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90
			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90
			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90
			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16
			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16
			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20					0x10
			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11				0x150
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL					0x400001c2
			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA					0x400001c2
		>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14				0x1c2
			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15				0x1c2
		>;
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03				0x1c0
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC			0xd6
			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK			0xd6
			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00			0xd6
			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00			0xd6
			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK			0xd6
			MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC			0xd6
			MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK			0xd6
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK				0x190
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD				0x1d0
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0				0x1d0
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1				0x1d0
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2				0x1d0
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3				0x1d0
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK				0x194
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD				0x1d4
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0				0x1d4
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1				0x1d4
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2				0x1d4
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3				0x1d4
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK				0x196
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD				0x1d6
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0				0x1d6
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1				0x1d6
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2				0x1d6
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3				0x1d6
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x190
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d0
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d0
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d0
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d0
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d0
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d0
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d0
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d0
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d0
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x194
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d4
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d4
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d4
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d4
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d4
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d4
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d4
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d4
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d4
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x196
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d6
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d6
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d6
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d6
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d6
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d6
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d6
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d6
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d6
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B				0xc6
		>;
	};

	pinctrl_wifi: wifigrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07				0xc0 /* WIFI_EN  */
			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08				0xc0 /* WIFI_PWR */
		>;
	};

	pinctrl_bt: btgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06				0xc0 /* BT_EN  */
			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09				0xc0 /* BT_BUF */
		>;
	};
};