// SPDX-License-Identifier: (GPL-2.0 OR MIT)

#include <dt-bindings/features/imx8m.h>

/ {
	remoteproc_cm7: remoteproc-cm7 {
		compatible = "fsl,imx8mp-cm7";
		clocks = <&clk IMX8MP_CLK_M7_CORE>;
		syscon = <&src>;
	};

	aliases {
		pwm0 = &pwm1;
		pwm1 = &pwm2;
		pwm2 = &pwm3;
		pwm3 = &pwm4;
	};

	chosen {
		barebox,bootsource-mmc0 = &usdhc1;
		barebox,bootsource-mmc1 = &usdhc2;
		barebox,bootsource-mmc2 = &usdhc3;
	};
};

/*
 * The DSP reserved memory will collide with the Barebox malloc area for some
 * DRAM sizes, even though the DSP itself is disabled in most configurations.
 */
/delete-node/ &dsp_reserved;
&dsp {
	barebox,feature-gates = <&feat IMX8M_FEAT_DSP>;
	/delete-property/ memory-region;
	status = "disabled";
};

&edacmc {
	compatible = "fsl,imx8mp-ddrc", "fsl,imx8m-ddrc", "snps,ddrc-3.80a";
};

feat: &ocotp {
	#feature-cells = <1>;
	barebox,feature-controller;
};

&pgc_gpu2d {
	barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
};

&pgc_gpu3d {
	barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
};

&pgc_gpumix {
	barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
};

&mipi_dsi {
	barebox,feature-gates = <&feat IMX8M_FEAT_MIPI_DSI>;
};

&lcdif1 {
	barebox,feature-gates = <&feat IMX8M_FEAT_MIPI_DSI>;
};

&gpu3d {
	barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
};

&gpu2d {
	barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
};

&pgc_vpumix {
	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
};

&pgc_vpu_g1 {
	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
};

&pgc_vpu_g2 {
	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
};

&pgc_vpu_vc8000e {
	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
};

&vpu_g1 {
	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
};

&vpu_g2 {
	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
};

&vpumix_blk_ctrl {
	barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
};

&pgc_mlmix {
	barebox,feature-gates = <&feat IMX8M_FEAT_NPU>;
};

&lcdif2 {
	barebox,feature-gates = <&feat IMX8M_FEAT_LVDS>;
};

&lvds_bridge {
	barebox,feature-gates = <&feat IMX8M_FEAT_LVDS>;
};