// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2019-2020 MNT Research GmbH
 * Copyright 2020 Lucas Stach <dev@lynxeye.de>
 */

/dts-v1/;

#include <arm64/freescale/imx8mq.dtsi>
#include "imx8mq.dtsi"
#include "imx8mq-ddrc.dtsi"

/ {
	model = "MNT Reform2";
	compatible = "mntre,reform2", "fsl,imx8mq";

	chosen {
		stdout-path = &uart1;

		environment-emmc {
			compatible = "barebox,environment";
			device-path = &usdhc1, "partname:barebox-environment";
			status = "disabled";
		};

		environment-sd {
			compatible = "barebox,environment";
			device-path = &usdhc2, "partname:barebox-environment";
			status = "disabled";
		};
	};

	pcie1_refclk: pcie1-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@4 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <4>;
			interrupts = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
		};
	};
};

&ocotp {
	barebox,provide-mac-address = <&fec1 0x640>;
};

&pcie1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie1>;
	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
		 <&pcie1_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&usb3_phy0 {
	status = "okay";
};

&usb3_phy1 {
	status = "okay";
};

&usb_dwc3_0 {
	status = "okay";
	dr_mode = "host";
};

&usb_dwc3_1 {
	status = "okay";
	dr_mode = "host";
};

&usdhc1 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-mmc-hs400;
	non-removable;
	no-sd;
	no-sdio;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
		label = "barebox";
		reg = <0x0 0xe0000>;
	};

	partition@e0000 {
		label = "barebox-environment";
		reg = <0xe0000 0x20000>;
	};
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	no-1-8-v;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
		label = "barebox";
		reg = <0x0 0xe0000>;
	};

	partition@e0000 {
		label = "barebox-environment";
		reg = <0xe0000 0x20000>;
	};
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0xd1
			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0xd1
			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x1
			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x1
		>;
	};

	pinctrl_pcie1: pcie1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x16
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x45
			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x45
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
			MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10		0x41
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x03
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc
		>;
	};

	pinctrl_wdog: wdog1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
		>;
	};
};