/* * arch/arm/mach-at91/at91rm9200_devices.c * * Copyright (C) 2005 Thibaut VARENE * Copyright (C) 2005 David Brownell * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * */ #include #include #include #include #include #include #include #include "generic.h" void at91_add_device_sdram(u32 size) { arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size); } /* -------------------------------------------------------------------- * USB Host * -------------------------------------------------------------------- */ #if defined(CONFIG_USB_OHCI) void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) { if (!data) return; add_generic_device("at91_ohci", -1, NULL, AT91RM9200_UHP_BASE, 1024 * 1024, IORESOURCE_MEM, data); } #else void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {} #endif /* -------------------------------------------------------------------- * Ethernet * -------------------------------------------------------------------- */ #if defined(CONFIG_DRIVER_NET_AT91_ETHER) void __init at91_add_device_eth(struct at91_ether_platform_data *data) { if (!data) return; /* Pins used for MII and RMII */ at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */ at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */ at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */ at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */ at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */ at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */ at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */ if (!(data->flags & AT91SAM_ETHER_RMII)) { at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */ at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */ at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */ at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */ at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */ at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */ at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */ } add_generic_device("at91_ether", 0, NULL, AT91_VA_BASE_EMAC, 0x1000, IORESOURCE_MEM, data); } #else void __init at91_add_device_eth(struct at91_ether_platform_data *data) {} #endif /* -------------------------------------------------------------------- * NAND / SmartMedia * -------------------------------------------------------------------- */ #if defined(CONFIG_NAND_ATMEL) void __init at91_add_device_nand(struct atmel_nand_data *data) { unsigned int csa; if (!data) return; /* enable the address range of CS3 */ csa = at91_sys_read(AT91_EBI_CSA); at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA); /* set the bus interface characteristics */ at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN | AT91_SMC_NWS_(5) | AT91_SMC_TDF_(1) | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */ | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */ ); /* enable pin */ if (data->enable_pin) at91_set_gpio_output(data->enable_pin, 1); /* ready/busy pin */ if (data->rdy_pin) at91_set_gpio_input(data->rdy_pin, 1); /* card detect pin */ if (data->det_pin) at91_set_gpio_input(data->det_pin, 1); at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */ at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */ add_generic_device("atmel_nand", 0, NULL, AT91_CHIPSELECT_3, 0x10, IORESOURCE_MEM, data); } #else void __init at91_add_device_nand(struct atmel_nand_data *data) {} #endif /* -------------------------------------------------------------------- * UART * -------------------------------------------------------------------- */ static inline void configure_dbgu_pins(void) { at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */ at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */ } static inline void configure_usart0_pins(unsigned pins) { at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */ at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */ if (pins & ATMEL_UART_CTS) at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */ if (pins & ATMEL_UART_RTS) { /* * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21. * We need to drive the pin manually. Default is off (RTS is active low). */ at91_set_gpio_output(AT91_PIN_PA21, 1); } } static inline void configure_usart1_pins(unsigned pins) { at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */ at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */ if (pins & ATMEL_UART_RI) at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */ if (pins & ATMEL_UART_DTR) at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */ if (pins & ATMEL_UART_DCD) at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */ if (pins & ATMEL_UART_CTS) at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */ if (pins & ATMEL_UART_DSR) at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */ if (pins & ATMEL_UART_RTS) at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */ } static inline void configure_usart2_pins(unsigned pins) { at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */ at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */ if (pins & ATMEL_UART_CTS) at91_set_B_periph(AT91_PIN_PA30, 0); /* CTS2 */ if (pins & ATMEL_UART_RTS) at91_set_B_periph(AT91_PIN_PA31, 0); /* RTS2 */ } static inline void configure_usart3_pins(unsigned pins) { at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */ at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */ if (pins & ATMEL_UART_CTS) at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS3 */ if (pins & ATMEL_UART_RTS) at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */ } void __init at91_register_uart(unsigned id, unsigned pins) { resource_size_t start; switch (id) { case 0: /* DBGU */ configure_dbgu_pins(); start = AT91_BASE_SYS + AT91_DBGU; id = 0; break; case AT91RM9200_ID_US0: configure_usart0_pins(pins); start = AT91RM9200_BASE_US0; id = 1; break; case AT91RM9200_ID_US1: configure_usart1_pins(pins); start = AT91RM9200_BASE_US1; id = 2; break; case AT91RM9200_ID_US2: configure_usart2_pins(pins); start = AT91RM9200_BASE_US2; id = 3; break; case AT91RM9200_ID_US3: configure_usart3_pins(pins); start = AT91RM9200_BASE_US3; id = 4; break; default: return; } add_generic_device("atmel_usart", id, NULL, start, 4096, IORESOURCE_MEM, NULL); }