/* * Memory Setup stuff - taken from blob memsetup.S * * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) * * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include #include #include #include #include #include #include #include #include #include _TEXT_BASE: .word TEXT_BASE .globl board_init_lowlevel .type board_init_lowlevel,function board_init_lowlevel: mov r5, pc /* r5 = POS1 + 4 current */ POS1: ldr r0, =POS1 /* r0 = POS1 compile */ ldr r2, _TEXT_BASE sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */ sub r5, r5, r0 /* r0 = TEXT_BASE-1 */ sub r5, r5, #4 /* r1 = text base - current */ /* memory control configuration 1 */ ldr r0, =SMRDATA ldr r2, =SMRDATA1 ldr r1, _TEXT_BASE sub r0, r0, r1 sub r2, r2, r1 add r0, r0, r5 add r2, r2, r5 0: /* the address */ ldr r1, [r0], #4 /* the value */ ldr r3, [r0], #4 str r3, [r1] cmp r2, r0 bne 0b /* ---------------------------------------------------------------------------- * PMC Init Step 1. * ---------------------------------------------------------------------------- * - Check if the PLL is already initialized * ---------------------------------------------------------------------------- */ ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) ldr r0, [r1] and r0, r0, #3 cmp r0, #0 bne PLL_setup_end /* --------------------------------------------------------------------------- * - Enable the Main Oscillator * --------------------------------------------------------------------------- */ ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) /* Main oscillator Enable register PMC_MOR: */ ldr r0, =CONFIG_SYS_MOR_VAL str r0, [r1] /* Reading the PMC Status to detect when the Main Oscillator is enabled */ mov r4, #AT91_PMC_MOSCS MOSCS_Loop: ldr r3, [r2] and r3, r4, r3 cmp r3, #AT91_PMC_MOSCS bne MOSCS_Loop /* ---------------------------------------------------------------------------- * PMC Init Step 2. * ---------------------------------------------------------------------------- * Setup PLLA * ---------------------------------------------------------------------------- */ ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR) ldr r0, =CONFIG_SYS_PLLAR_VAL str r0, [r1] /* Reading the PMC Status register to detect when the PLLA is locked */ mov r4, #AT91_PMC_LOCKA MOSCS_Loop1: ldr r3, [r2] and r3, r4, r3 cmp r3, #AT91_PMC_LOCKA bne MOSCS_Loop1 /* ---------------------------------------------------------------------------- * PMC Init Step 3. * ---------------------------------------------------------------------------- * - Switch on the Main Oscillator * ---------------------------------------------------------------------------- */ ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) /* -Master Clock Controller register PMC_MCKR */ ldr r0, =CONFIG_SYS_MCKR1_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ mov r4, #AT91_PMC_MCKRDY MCKRDY_Loop: ldr r3, [r2] and r3, r4, r3 cmp r3, #AT91_PMC_MCKRDY bne MCKRDY_Loop ldr r0, =CONFIG_SYS_MCKR2_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ mov r4, #AT91_PMC_MCKRDY MCKRDY_Loop1: ldr r3, [r2] and r3, r4, r3 cmp r3, #AT91_PMC_MCKRDY bne MCKRDY_Loop1 PLL_setup_end: /* ---------------------------------------------------------------------------- * - memory control configuration 2 * ---------------------------------------------------------------------------- */ ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR) ldr r1, [r0] cmp r1, #0 bne SDRAM_setup_end ldr r0, =SMRDATA1 ldr r2, =SMRDATA2 ldr r1, _TEXT_BASE sub r0, r0, r1 sub r2, r2, r1 add r0, r0, r5 add r2, r2, r5 2: /* the address */ ldr r1, [r0], #4 /* the value */ ldr r3, [r0], #4 str r3, [r1] cmp r2, r0 bne 2b SDRAM_setup_end: /* everything is fine now */ mov pc, lr .ltorg SMRDATA: .word (AT91_BASE_SYS + AT91_WDT_MR) .word CONFIG_SYS_WDTC_WDMR_VAL /* configure PIOx as EBI0 D[16-31] */ #if defined(CONFIG_ARCH_AT91SAM9263) .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR) .word CONFIG_SYS_PIOD_PDR_VAL1 .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR) .word CONFIG_SYS_PIOD_PPUDR_VAL .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) .word CONFIG_SYS_PIOD_PPUDR_VAL #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261) .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR) .word CONFIG_SYS_PIOC_PDR_VAL1 .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR) .word CONFIG_SYS_PIOC_PPUDR_VAL #endif #if defined(AT91_MATRIX_EBI0CSA) .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA) .word CONFIG_SYS_MATRIX_EBI0CSA_VAL #else /* AT91_MATRIX_EBICSA */ .word (AT91_BASE_SYS + AT91_MATRIX_EBICSA) .word CONFIG_SYS_MATRIX_EBICSA_VAL #endif /* flash */ .word (AT91_BASE_SYS + AT91_SMC_MODE(0)) .word CONFIG_SYS_SMC0_MODE0_VAL .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0)) .word CONFIG_SYS_SMC0_CYCLE0_VAL .word (AT91_BASE_SYS + AT91_SMC_PULSE(0)) .word CONFIG_SYS_SMC0_PULSE0_VAL .word (AT91_BASE_SYS + AT91_SMC_SETUP(0)) .word CONFIG_SYS_SMC0_SETUP0_VAL SMRDATA1: .word (AT91_BASE_SYS + AT91_SDRAMC_MR) .word CONFIG_SYS_SDRC_MR_VAL1 .word (AT91_BASE_SYS + AT91_SDRAMC_TR) .word CONFIG_SYS_SDRC_TR_VAL1 .word (AT91_BASE_SYS + AT91_SDRAMC_CR) .word CONFIG_SYS_SDRC_CR_VAL .word (AT91_BASE_SYS + AT91_SDRAMC_MDR) .word CONFIG_SYS_SDRC_MDR_VAL .word (AT91_BASE_SYS + AT91_SDRAMC_MR) .word CONFIG_SYS_SDRC_MR_VAL2 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL1 .word (AT91_BASE_SYS + AT91_SDRAMC_MR) .word CONFIG_SYS_SDRC_MR_VAL3 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL2 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL3 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL4 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL5 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL6 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL7 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL8 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL9 .word (AT91_BASE_SYS + AT91_SDRAMC_MR) .word CONFIG_SYS_SDRC_MR_VAL4 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL10 .word (AT91_BASE_SYS + AT91_SDRAMC_MR) .word CONFIG_SYS_SDRC_MR_VAL5 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL11 .word (AT91_BASE_SYS + AT91_SDRAMC_TR) .word CONFIG_SYS_SDRC_TR_VAL2 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL12 /* User reset enable*/ .word (AT91_BASE_SYS + AT91_RSTC_MR) .word CONFIG_SYS_RSTC_RMR_VAL #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP /* MATRIX_MCFG - REMAP all masters */ .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0) .word 0x1FF #endif SMRDATA2: .word 0