/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef __MACH_IMX8MM_REGS_H
#define __MACH_IMX8MM_REGS_H

#include <mach/imx8m-regs.h>

#define MX8MM_M4_BOOTROM_BASE_ADDR	0x007e0000

#define MX8MM_GPIO1_BASE_ADDR		0x30200000
#define MX8MM_GPIO2_BASE_ADDR		0x30210000
#define MX8MM_GPIO3_BASE_ADDR		0x30220000
#define MX8MM_GPIO4_BASE_ADDR		0x30230000
#define MX8MM_GPIO5_BASE_ADDR		0x30240000
#define MX8MM_WDOG1_BASE_ADDR		0x30280000
#define MX8MM_WDOG2_BASE_ADDR		0x30290000
#define MX8MM_WDOG3_BASE_ADDR		0x302a0000
#define MX8MM_IOMUXC_BASE_ADDR		0x30330000
#define MX8MM_IOMUXC_GPR_BASE_ADDR	0x30340000
#define MX8MM_OCOTP_BASE_ADDR		0x30350000
#define MX8MM_ANATOP_BASE_ADDR		0x30360000
#define MX8MM_CCM_BASE_ADDR		0x30380000
#define MX8MM_SRC_BASE_ADDR		0x30390000
#define MX8MM_GPC_BASE_ADDR		0x303a0000
#define MX8MM_SYSCNT_RD_BASE_ADDR	0x306a0000
#define MX8MM_SYSCNT_CMP_BASE_ADDR	0x306b0000
#define MX8MM_SYSCNT_CTRL_BASE_ADDR	0x306c0000
#define MX8MM_I2C1_BASE_ADDR		0x30a20000
#define MX8MM_I2C2_BASE_ADDR		0x30a30000
#define MX8MM_I2C3_BASE_ADDR		0x30a40000
#define MX8MM_I2C4_BASE_ADDR		0x30a50000
#define MX8MM_USDHC1_BASE_ADDR		0x30b40000
#define MX8MM_USDHC2_BASE_ADDR		0x30b50000
#define MX8MM_USDHC3_BASE_ADDR		0x30b60000
#define MX8MM_USB1_BASE_ADDR		0x32e40000
#define MX8MM_USB2_BASE_ADDR		0x32e50000
#define MX8MM_TZASC_BASE_ADDR		0x32f80000
#define MX8MM_SRC_IPS_BASE_ADDR		0x30390000
#define MX8MM_SRC_DDRC_RCR_ADDR		0x30391000
#define MX8MM_SRC_DDRC2_RCR_ADDR	0x30391004
#define MX8MM_DDRC_DDR_SS_GPR0		0x3d000000
#define MX8MM_DDR_CSD1_BASE_ADDR	0x40000000

#endif /* __MACH_IMX8MM_REGS_H */