/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * VFxxx IOMUX register addresses definitions for use in DCD
 *
 * Copyright (C) 2018 Zodiac Inflight Innovations
 */

#define VF610_PAD_DDR_RESETB		0x4004821c
#define VF610_PAD_DDR_A15__DDR_A_15	0x40048220
#define VF610_PAD_DDR_A14__DDR_A_14	0x40048224
#define VF610_PAD_DDR_A13__DDR_A_13	0x40048228
#define VF610_PAD_DDR_A12__DDR_A_12	0x4004822c
#define VF610_PAD_DDR_A11__DDR_A_11	0x40048230
#define VF610_PAD_DDR_A10__DDR_A_10	0x40048234
#define VF610_PAD_DDR_A9__DDR_A_9	0x40048238
#define VF610_PAD_DDR_A8__DDR_A_8	0x4004823c
#define VF610_PAD_DDR_A7__DDR_A_7	0x40048240
#define VF610_PAD_DDR_A6__DDR_A_6	0x40048244
#define VF610_PAD_DDR_A5__DDR_A_5	0x40048248
#define VF610_PAD_DDR_A4__DDR_A_4	0x4004824c
#define VF610_PAD_DDR_A3__DDR_A_3	0x40048250
#define VF610_PAD_DDR_A2__DDR_A_2	0x40048254
#define VF610_PAD_DDR_A1__DDR_A_1	0x40048258
#define VF610_PAD_DDR_A0__DDR_A_0	0x4004825c
#define VF610_PAD_DDR_BA2__DDR_BA_2	0x40048260
#define VF610_PAD_DDR_BA1__DDR_BA_1	0x40048264
#define VF610_PAD_DDR_BA0__DDR_BA_0	0x40048268
#define VF610_PAD_DDR_CAS__DDR_CAS_B	0x4004826c
#define VF610_PAD_DDR_CKE__DDR_CKE_0	0x40048270
#define VF610_PAD_DDR_CLK__DDR_CLK_0	0x40048274
#define VF610_PAD_DDR_CS__DDR_CS_B_0	0x40048278
#define VF610_PAD_DDR_D15__DDR_D_15	0x4004827c
#define VF610_PAD_DDR_D14__DDR_D_14	0x40048280
#define VF610_PAD_DDR_D13__DDR_D_13	0x40048284
#define VF610_PAD_DDR_D12__DDR_D_12	0x40048288
#define VF610_PAD_DDR_D11__DDR_D_11	0x4004828c
#define VF610_PAD_DDR_D10__DDR_D_10	0x40048290
#define VF610_PAD_DDR_D9__DDR_D_9	0x40048294
#define VF610_PAD_DDR_D8__DDR_D_8	0x40048298
#define VF610_PAD_DDR_D7__DDR_D_7	0x4004829c
#define VF610_PAD_DDR_D6__DDR_D_6	0x400482a0
#define VF610_PAD_DDR_D5__DDR_D_5	0x400482a4
#define VF610_PAD_DDR_D4__DDR_D_4	0x400482a8
#define VF610_PAD_DDR_D3__DDR_D_3	0x400482ac
#define VF610_PAD_DDR_D2__DDR_D_2	0x400482b0
#define VF610_PAD_DDR_D1__DDR_D_1	0x400482b4
#define VF610_PAD_DDR_D0__DDR_D_0	0x400482b8
#define VF610_PAD_DDR_DQM1__DDR_DQM_1	0x400482bc
#define VF610_PAD_DDR_DQM0__DDR_DQM_0	0x400482c0
#define VF610_PAD_DDR_DQS1__DDR_DQS_1	0x400482c4
#define VF610_PAD_DDR_DQS0__DDR_DQS_0	0x400482c8
#define VF610_PAD_DDR_RAS__DDR_RAS_B	0x400482cc
#define VF610_PAD_DDR_WE__DDR_WE_B	0x400482d0
#define VF610_PAD_DDR_ODT1__DDR_ODT_0	0x400482d4
#define VF610_PAD_DDR_ODT0__DDR_ODT_1	0x400482d8

#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1	0x400482dc
#define VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0	0x400482e0