# SPDX-License-Identifier: GPL-2.0-only

if ARCH_SOCFPGA

config ARCH_TEXT_BASE
	hex
	default 0x0

config ARCH_SOCFPGA_XLOAD
	bool
	prompt "Build preloader image"

comment "Altera SoCFPGA System-on-Chip"

config ARCH_SOCFPGA_CYCLONE5
	bool
	select CPU_V7
	select HAVE_PBL_MULTI_IMAGES
	select OFDEVICE if !ARCH_SOCFPGA_XLOAD
	select OFTREE if !ARCH_SOCFPGA_XLOAD
	select GPIOLIB if !ARCH_SOCFPGA_XLOAD

config ARCH_SOCFPGA_ARRIA10
	bool
	select CPU_V7
	select ARM_USE_COMPRESSED_DTB
	select RESET_CONTROLLER
	select HAVE_PBL_MULTI_IMAGES
	select OFDEVICE
	select OFTREE

config MACH_SOCFPGA_ALTERA_SOCDK
	select ARCH_SOCFPGA_CYCLONE5
	bool "Altera SoCFPGA Development Kit"

config MACH_SOCFPGA_EBV_SOCRATES
	select ARCH_SOCFPGA_CYCLONE5
	bool "EBV Socrates"

config MACH_SOCFPGA_ENCLUSTRA_AA1
	select ARCH_SOCFPGA_ARRIA10
	bool "Enclustra AA1"

config MACH_SOCFPGA_REFLEX_ACHILLES
	select ARCH_SOCFPGA_ARRIA10
	bool "Reflex Achilles"

config MACH_SOCFPGA_TERASIC_DE0_NANO_SOC
	select ARCH_SOCFPGA_CYCLONE5
	bool "Terasic DE0-NANO-SoC aka Atlas"

config MACH_SOCFPGA_TERASIC_DE10_NANO
	select ARCH_SOCFPGA_CYCLONE5
	bool "Terasic DE10-NANO"

config MACH_SOCFPGA_TERASIC_SOCKIT
	select ARCH_SOCFPGA_CYCLONE5
	bool "Terasic SoCKit"

endif