#ifndef __MACH_SOCFPGA_REGS_H
#define __MACH_SOCFPGA_REGS_H

#define CYCLONE5_SDMMC_ADDRESS		0xff704000
#define CYCLONE5_QSPI_CTRL_ADDRESS	0xff705000
#define CYCLONE5_QSPI_DATA_ADDRESS	0xffa00000
#define CYCLONE5_FPGAMGRREGS_ADDRESS	0xff706000
#define CYCLONE5_GPIO0_BASE		0xff708000
#define CYCLONE5_GPIO1_BASE		0xff709000
#define CYCLONE5_GPIO2_BASE		0xff70A000
#define CYCLONE5_L3REGS_ADDRESS		0xff800000
#define CYCLONE5_FPGAMGRDATA_ADDRESS	0xffb90000
#define CYCLONE5_UART0_ADDRESS		0xffc02000
#define CYCLONE5_UART1_ADDRESS		0xffc03000
#define CYCLONE5_SDR_ADDRESS		0xffc20000
#define CYCLONE5_CLKMGR_ADDRESS		0xffd04000
#define CYCLONE5_RSTMGR_ADDRESS		0xffd05000
#define CYCLONE5_SYSMGR_ADDRESS		0xffd08000
#define CYCLONE5_SCANMGR_ADDRESS	0xfff02000
#define CYCLONE5_SMP_TWD_ADDRESS	0xfffec600

#endif /* __MACH_SOCFPGA_REGS_H */