/dts-v1/; / { model = "or1ksim"; compatible = "opencores,or1ksim"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&pic>; chosen { bootargs = "console=uart,mmio,0x90000000,115200"; }; memory { device_type = "memory"; reg = <0x00000000 0x02000000>; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "opencores,or1200-rtlsvn481"; reg = <0>; clock-frequency = <20000000>; }; }; /* * OR1K PIC is built into CPU and accessed via special purpose * registers. It is not addressable and, hence, has no 'reg' * property. */ pic: pic { compatible = "opencores,or1k-pic"; #interrupt-cells = <1>; interrupt-controller; }; serial0: serial@90000000 { compatible = "ns16550a"; reg = <0x90000000 0x100>; interrupts = <2>; clock-frequency = <50000000>; }; enet0: ethoc@92000000 { compatible = "opencores,ethoc"; reg = <0x92000000 0x100>; interrupts = <4>; }; };