# SPDX-License-Identifier: GPL-2.0-only config RISCV def_bool y select GENERIC_FIND_NEXT_BIT select GPIOLIB select OFTREE select OFDEVICE select COMMON_CLK select COMMON_CLK_OF_PROVIDER select HAS_DMA select ARCH_DMA_DEFAULT_COHERENT select HAVE_PBL_IMAGE select HAVE_PBL_MULTI_IMAGES select HAVE_IMAGE_COMPRESSION select ARCH_HAS_SJLJ select HAS_KALLSYMS select RISCV_TIMER if RISCV_SBI select HW_HAS_PCI config ARCH_TEXT_BASE hex default 0x0 choice prompt "Base ISA" default ARCH_RV32I config ARCH_RV32I bool "RV32I" select CPU_SUPPORTS_32BIT_KERNEL select GENERIC_LIB_ASHLDI3 select GENERIC_LIB_ASHRDI3 select GENERIC_LIB_LSHRDI3 select 32BIT config ARCH_RV64I bool "RV64I" select CPU_SUPPORTS_64BIT_KERNEL select 64BIT endchoice source "arch/riscv/Kconfig.socs" config CPU_SUPPORTS_32BIT_KERNEL bool config CPU_SUPPORTS_64BIT_KERNEL bool config PHYS_ADDR_T_64BIT bool config 32BIT bool depends on CPU_SUPPORTS_32BIT_KERNEL config 64BIT bool depends on CPU_SUPPORTS_64BIT_KERNEL select ARCH_DMA_ADDR_T_64BIT select PHYS_ADDR_T_64BIT config BOARD_RISCV_GENERIC_DT select BOARD_GENERIC_DT bool "Build generic RISC-V device tree 2nd stage image" help This enables compilation of a generic image that can be started 2nd stage from barebox or from qemu. It picks up a device tree passed in a1 like the Kernel does, so it could be used anywhere where a Kernel image could be used. The image will be called images/barebox-dt-2nd.img menu "RISC-V specific settings" config RISCV_OPTIMZED_STRING_FUNCTIONS bool "use assembler optimized string functions" help Say yes here to use assembler optimized memcpy / memset functions. These functions work faster than the normal versions but increase your binary size. config RISCV_EXCEPTIONS bool "enable exception handling support" default y select ARCH_HAS_DATA_ABORT_MASK config RISCV_UNWIND bool "enable stack unwinding support" select ARCH_HAS_STACK_DUMP select ARCH_WANT_FRAME_POINTERS help This option enables stack unwinding support in barebox using the information automatically generated by the compiler. The resulting kernel image is slightly bigger but the performance is not affected. config HAS_NMON bool config NMON bool "nmon" depends on HAS_NMON depends on DEBUG_LL help Say yes here to add the nmon to pbl. nmon -- nano-monitor program for the RISC-V processors. It can operate with NO working RAM, using only the processor registers. config NMON_HELP bool "nmon help message" depends on NMON help Say yes here to get the nmon commands message on every nmon start. # selected by boards where barebox runs in machine mode config RISCV_M_MODE bool # selected by boards where barebox runs in supervisor mode config RISCV_S_MODE bool config RISCV_MULTI_MODE def_bool RISCV_S_MODE && RISCV_M_MODE config RISCV_SBI def_bool RISCV_S_MODE endmenu