# SPDX-License-Identifier: GPL-2.0-only

menu "SoC selection"

config SOC_ERIZO
	bool "Erizo SoC"
	depends on ARCH_RV32I
	select HAS_DEBUG_LL
	select HAS_NMON
	select USE_COMPRESSED_DTB
	select RISCV_M_MODE
	select RISCV_TIMER

config BOARD_ERIZO_GENERIC
	depends on SOC_ERIZO
	def_bool y

config SOC_VIRT
	bool "QEMU Virt Machine"
	select RISCV_S_MODE
	select BOARD_RISCV_GENERIC_DT
	select HAS_CACHE
	select HAS_DEBUG_LL
	help
	  Generates an image tht can be be booted by QEMU. The image is called
	  barebox-dt-2nd.img

config BOARD_RISCV_VIRT
	depends on SOC_VIRT
	bool "QEMU Virt Machine"
	select OF_OVERLAY
	select BOARD_QEMU_VIRT
	default y
	help
	  Enables environment and state on top of QEMU RISC-V Virt machine
	  cfi-flash.

config BOARD_RISCVEMU
	depends on SOC_VIRT
	bool "TinyEMU Virt Machine (riscvemu)"
	select OF_OVERLAY
	default y
	help
	  TinyEMU's Virt machine differs from QEMU in poweroff and restart
	  mechanisms. This adds the necessary support.

config CPU_SIFIVE
	bool
	select HAS_CACHE

config SOC_SIFIVE
	bool "SiFive SoCs"
	select CPU_SIFIVE
	select RISCV_S_MODE
	select CLK_SIFIVE
	select CLK_SIFIVE_PRCI
	select RISCV_TIMER
	select HAS_MACB
	select HAS_DEBUG_LL
	help
	  This enables support for SiFive SoC platform hardware.

if SOC_SIFIVE

config BOARD_HIFIVE
	bool "HiFive"
	depends on ARCH_RV64I
	select USE_COMPRESSED_DTB

endif

config SOC_STARFIVE
	bool "StarFive SoCs"
	select ARCH_HAS_RESET_CONTROLLER
	select RISCV_S_MODE
	select HAS_DEBUG_LL
	select HAS_NMON
	help
	  This enables support for SiFive SoC platform hardware.

if SOC_STARFIVE

config SOC_STARFIVE_JH71XX
	bool
	select CPU_SIFIVE

config SOC_STARFIVE_JH7100
	bool
	select SOC_STARFIVE_JH71XX
	select SIFIVE_L2
	select OF_DMA_COHERENCY
	help
	  Unlike JH7110 and later, CPU on the JH7100 are not cache-coherent
	  with respect to DMA masters like GMAC and DW MMC controller.
	  Select this if barebox needs to do DMA on this SoC.

config BOARD_BEAGLEV
	bool "BeagleV"
	depends on ARCH_RV64I
	select SOC_STARFIVE_JH71XX
	select USE_COMPRESSED_DTB

config BOARD_BEAGLEV_BETA
	bool "BeagleV Beta (with JH7100)"
	depends on BOARD_BEAGLEV
	select SOC_STARFIVE_JH7100
	help
	  Select this for hardware using the earlier JH7100 SoC. The JH7110
	  used with later production runs is cache-coherent and thus can do
	  without the special DMA handling enabled by this option. It's safe
	  to enable this option for other SoCs.

endif

config SOC_ALLWINNER_SUN20I
	bool "Allwinner Sun20i SoCs"
	depends on ARCH_RV64I
	select HAS_DEBUG_LL
	select HAS_CACHE

if SOC_ALLWINNER_SUN20I

config BOARD_ALLWINNER_D1
	bool "Allwinner D1 Nezha"
	select RISCV_S_MODE
	select RISCV_M_MODE
	def_bool y

endif

comment "CPU features"

config SIFIVE_L2
	bool "SiFive L2 cache controller"
	depends on CPU_SIFIVE

config SOC_LITEX
	bool "LiteX SoCs"
	depends on ARCH_RV32I
	select HAS_DEBUG_LL
	select HAS_NMON
	select USE_COMPRESSED_DTB
	select RISCV_TIMER

config BOARD_LITEX_LINUX
	bool "litex linux board"
	depends on SOC_LITEX
	select RISCV_M_MODE
	def_bool y

endmenu