// SPDX-License-Identifier: GPL-2.0

#include <dt-bindings/reset-controller/starfive-jh7100.h>
#include <dt-bindings/clock/starfive-jh7100.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "starfive,jh7100";

	aliases {
		spi0 = &qspi;
		mmc0 = &sdio0;
		mmc1 = &sdio1;
		usb0 = &usb3;
	};

	chosen {
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "sifive,u74-mc", "riscv";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			reg = <0>;
			riscv,isa = "rv64imafdc";
			starfive,itim = <&itim0>;
			status = "okay";
			tlb-split;
			cpu0_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};

		cpu@1 {
			compatible = "sifive,u74-mc", "riscv";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			reg = <1>;
			riscv,isa = "rv64imafdc";
			starfive,itim = <&itim1>;
			status = "okay";
			tlb-split;
			cpu1_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};
	};

	osc_sys: clock-osc-sys {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
		clock-output-names = "osc_sys";
	};

	osc_aud: clock-osc-audio {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
		clock-output-names = "osc_aud";
	};

	i2c0clk: i2c0clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <49500000>;
		clock-output-names = "i2c0clk";
	};

	i2c2clk: i2c2clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <49500000>;
		clock-output-names = "i2c2clk";
	};

	axiclk: axiclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <500000000>;
		clock-output-names = "axiclk";
	};

	ahb0clk: ahb0clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <250000000>;
	};

	apb1clk: apb1clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <125000000>;
	};

	apb2clk: apb2clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <125000000>;
	};

	jpuclk: jpuclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <333333333>;
	};

	vpuclk: vpuclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <400000000>;
	};

	qspi_clk: qspi-clk@0 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <50000000>;
	};

	uartclk: uartclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <100000000>;
	};

	hs_uartclk: hs_uartclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <74250000>;
	};

	spiclk: spiclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <50000000>;
	};

	pwmclk: pwmclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <125000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x0 0x28000000>;
			alignment = <0x0 0x1000>;
			alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
			linux,cma-default;
		};

		jpu_reserved: framebuffer@c9000000 {
			reg = <0x0 0xc9000000 0x0 0x4000000>;
		};

		nvdla_reserved:framebuffer@d0000000 {
			reg = <0x0 0xd0000000 0x0 0x28000000>;
		};

		vin_reserved: framebuffer@f9000000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0x0 0xf9000000 0x0 0x1000000>;
		};

		sffb_reserved: framebuffer@fb000000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0x0 0xfb000000 0x0 0x2000000>;
		};
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		#clock-cells = <1>;
		compatible = "simple-bus";
		ranges;

		intram0: sram@18000000 {
			compatible = "mmio-sram";
			reg = <0x0 0x18000000 0x0 0x20000>;
		};

		intram1: sram@18080000 {
			compatible = "mmio-sram";
			reg = <0x0 0x18080000 0x0 0x8000>;
		};

		ccache: cache-controller@2010000 {
			cache-block-size = <64>;
			cache-level = <2>;
			cache-sets = <2048>;
			cache-size = <2097152>;
			cache-unified;
			compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
			interrupt-parent = <&plic>;
			interrupts = <128 131 129 130>;
			/*next-level-cache = <&L40 &L36>;*/
			reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
			reg-names = "control", "sideband";
		};

		dtim: dtim@1000000 {
			compatible = "starfive,dtim0";
			reg = <0x0 0x1000000 0x0 0x2000>;
			reg-names = "mem";
		};

		itim0: itim@1808000 {
			compatible = "starfive,itim0";
			reg = <0x0 0x1808000 0x0 0x8000>;
			reg-names = "mem";
		};

		itim1: itim@1820000 {
			compatible = "starfive,itim0";
			reg = <0x0 0x1820000 0x0 0x8000>;
			reg-names = "mem";
		};

		clint: clint@2000000 {
			#interrupt-cells = <1>;
			compatible = "riscv,clint0";
			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7>;
			reg = <0x0 0x2000000 0x0 0x10000>;
			reg-names = "control";
		};

		plic: plic@c000000 {
			#interrupt-cells = <1>;
			compatible = "riscv,plic0";
			interrupt-controller;
			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9 &cpu1_intc 11 &cpu1_intc 9>;
			reg = <0x0 0xc000000 0x0 0x4000000>;
			reg-names = "control";
			riscv,max-priority = <7>;
			riscv,ndev = <127>;
		};

		sysmain: syscon@11850000 {
			compatible = "syscon";
			reg = <0x0 0x11850000 0x0 0x4000>;
		};

		pinconf: pinctrl@11858000 {
			compatible = "pinctrl-single";
			reg = <0x0 0x11858000 0x0 0x4000>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0xffffffff>;
		};

		uart0: hs_serial@11870000 {
			compatible = "snps,dw-apb-uart";
			interrupt-parent = <&plic>;
			interrupts = <92>;
			reg = <0x0 0x11870000 0x0 0x10000>;
			reg-io-width = <4>;
			reg-shift = <2>;
			clocks = <&hs_uartclk>, <&apb1clk>;
			clock-names = "baudclk", "apb_pclk";
			current-clock = <74250000>;
			current-speed = <115200>;
			status = "disabled";
		};

		uart1: hs_serial@11880000 {
			compatible = "snps,dw-apb-uart";
			interrupt-parent = <&plic>;
			interrupts = <93>;
			reg = <0x0 0x11880000 0x0 0x10000>;
			reg-io-width = <4>;
			reg-shift = <2>;
			clocks = <&hs_uartclk>, <&apb1clk>;
			clock-names = "baudclk", "apb_pclk";
			current-clock = <74250000>;
			current-speed = <115200>;
			status = "disabled";
		};

		uart2: serial@12430000 {
			compatible = "snps,dw-apb-uart";
			interrupt-parent = <&plic>;
			interrupts = <72>;
			reg = <0x0 0x12430000 0x0 0x10000>;
			reg-io-width = <4>;
			reg-shift = <2>;
			clocks = <&uartclk>, <&apb2clk>;
			clock-names = "baudclk", "apb_pclk";
			current-clock = <100000000>;
			current-speed = <115200>;
			status = "disabled";
		};

		uart3: serial@12440000 {
			compatible = "snps,dw-apb-uart", "starfive,uart0";
			interrupt-parent = <&plic>;
			interrupts = <73>;
			reg = <0x0 0x12440000 0x0 0x10000>;
			reg-io-width = <4>;
			reg-shift = <2>;
			clocks = <&uartclk>, <&apb2clk>;
			clock-names = "baudclk", "apb_pclk";
			current-clock = <100000000>;
			current-speed = <115200>;
			status = "disabled";
		};

		nne50: nne@10800000 {
			compatible = "starfive,nne50";
			reg = <0x0 0x10800000 0x0 0x10000>;
			resets = <&rstgen RSTN_DLA_AXI>,
				<&rstgen RSTN_DLANOC_AXI>,
				<&rstgen RSTN_DLA_APB>,
				<&rstgen RSTN_NNENOC_AXI>,
				<&rstgen RSTN_DLASLV_AXI>;

			assigned-clocks = <&clkgen CLK_NNE_BUS>;
			assigned-clocks-parents = <&clkgen CLK_CPU_AXI>;
			status = "okay";
		};

		dma2p: sgdma2p@100b0000 {
			compatible = "starfive,axi-dma", "snps,axi-dma-1.01a";
			reg = <0x0 0x100b0000 0x0 0x10000>;
			clocks = <&axiclk>, <&ahb0clk>;
			clock-names = "core-clk", "cfgr-clk";
			resets = <&rstgen RSTN_DMA2PNOC_AXI>, <&rstgen RSTN_SGDMA2P_AXI>, <&rstgen RSTN_SGDMA2P_AHB>;
			reset-names = "noc", "axi", "ahb";
			interrupt-parent = <&plic>;
			interrupts = <2>;
			dma-channels = <4>;
			snps,dma-masters = <1>;
			snps,data-width = <4>;
			snps,block-size = <4096 4096 4096 4096>;
			snps,priority = <0 1 2 3>;
			snps,axi-max-burst-len = <128>;
			status = "okay";
		};

		dma1p: sgdma1p@10500000 {
			compatible = "starfive,axi-dma", "snps,axi-dma-1.01a";
			reg = <0x0 0x10500000 0x0 0x10000>;
			clocks = <&axiclk>, <&ahb0clk>;
			clock-names = "core-clk", "cfgr-clk";
			resets = <&rstgen RSTN_SGDMA1P_AXI>;
			interrupt-parent = <&plic>;
			interrupts = <1>;
			dma-channels = <16>;
			snps,dma-masters = <1>;
			snps,data-width = <3>;
			snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
			snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
			snps,axi-max-burst-len = <64>;
			status = "okay";
		};

		usb3: usb@104c0000 {
			compatible = "cdns,usb3";
			reg = <0x0 0x104c0000 0x0 0x10000>,	// memory area for HOST registers
			      <0x0 0x104d0000 0x0 0x10000>,	// memory area for DEVICE registers
			      <0x0 0x104e0000 0x0 0x10000>;	// memory area for OTG/DRD registers
			reg-names = "otg", "xhci", "dev";
			interrupt-parent = <&plic>;
			interrupts = <43>, <44>, <52>;
			interrupt-names = "otg",
					"host",
					"peripheral";
			phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
			maximum-speed = "super-speed";
			status = "disabled";
		};

		gpio: gpio@11910000 {
			compatible = "starfive,gpio0";
			interrupt-parent = <&plic>;
			interrupts = <32>;
			resets = <&rstgen RSTN_GPIO_APB>;
			clocks = <&clkgen CLK_GPIO_APB>;
			reg = <0x0 0x11910000 0x0 0x10000>;
			reg-names = "control";
			interrupt-controller;
			#gpio-cells = <2>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0xffffffff>;
		};

		i2c0: i2c@118b0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x0 0x118b0000 0x0 0x10000>;
			interrupt-parent = <&plic>;
			interrupts = <96>;
			clocks = <&i2c0clk>;
			clock-frequency = <100000>;
			i2c-sda-hold-time-ns = <300>;
			i2c-sda-falling-time-ns = <500>;
			i2c-scl-falling-time-ns = <500>;
			scl-gpio = <&gpio 62 0>;
			sda-gpio = <&gpio 61 0>;
			status = "disabled";
		};

		i2c1: i2c@118c0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x0 0x118c0000 0x0 0x10000>;
			interrupt-parent = <&plic>;
			interrupts = <97>;
			clocks = <&i2c0clk>;
			clock-frequency = <400000>;
			i2c-sda-hold-time-ns = <300>;
			i2c-sda-falling-time-ns = <100>;
			i2c-scl-falling-time-ns = <100>;
			scl-gpio = <&gpio 47 0>;
			sda-gpio = <&gpio 48 0>;
			status = "disabled";
		};

		i2c2: i2c@12450000 {
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x0 0x12450000 0x0 0x10000>;
			interrupt-parent = <&plic>;
			interrupts = <74>;
			clocks = <&i2c2clk>;
			clock-frequency = <100000>;
			i2c-sda-hold-time-ns = <300>;
			i2c-sda-falling-time-ns = <500>;
			i2c-scl-falling-time-ns = <500>;
			scl-gpio = <&gpio 60 0>;
			sda-gpio = <&gpio 59 0>;
			status = "disabled";
		};

		trng: trng@118d0000 {
			compatible = "starfive,vic-rng";
			reg = <0x0 0x118d0000 0x0 0x10000>;
			interrupt-parent = <&plic>;
			interrupts = <98>;
			clocks = <&clkgen CLK_TRNG_APB>;
			resets = <&rstgen RSTN_TRNG_APB>;
		};

		crypto: crypto@100d0000 {
			compatible = "starfive,vic-sec";
			reg = <0x0 0x100d0000 0x0 0x20000>,
			      <0x0 0x11800234 0x0 0xc>;
			reg-names = "secmem", "secclk";
			resets = <&rstgen RSTN_SEC_AHB>, <&rstgen RSTN_AES>,
			    <&rstgen RSTN_PKA>, <&rstgen RSTN_SHA>;
			interrupt-parent = <&plic>;
			interrupts = <31>;
			clocks = <&osc_sys>;
		};

		/* gmac device configuration */
		stmmac_axi_setup: stmmac-axi-config {
			snps,wr_osr_lmt = <0xf>;
			snps,rd_osr_lmt = <0xf>;
			snps,blen = <256 128 64 32 0 0 0>;
		};

		gmac: gmac@10020000 {
			compatible = "starfive,stmmac";
			reg = <0x0 0x10020000 0x0 0x10000>;
			interrupt-parent = <&plic>;
			interrupts = <6 7>;
			interrupt-names = "macirq", "eth_wake_irq";
			resets = <&rstgen RSTN_GMAC_AHB>;
			reset-names = "stmmaceth";
			clocks = <&clkgen CLK_GMAC_AHB>, <&clkgen CLK_GMAC_PTP_REF>,
				 <&clkgen CLK_GMAC_GTX>;
			clock-names = "stmmaceth", "ptp_ref", "tx";
			max-frame-size = <9000>;
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			rx-fifo-depth = <32768>;
			tx-fifo-depth = <16384>;
			snps,fixed-burst = <1>;
			snps,no-pbl-x8 = <1>;
			/*snps,force_sf_dma_mode;*/
			snps,force_thresh_dma_mode;
			snps,axi-config = <&stmmac_axi_setup>;
			starfive,sysmain = <&sysmain>;
		};

		nbdla: nvdla@11940000 {
			compatible = "nvidia,nvdla_os_initial";
			interrupt-parent = <&plic>;
			resets = <&rstgen RSTN_DLA_AXI>,
				<&rstgen RSTN_DLANOC_AXI>,
				<&rstgen RSTN_DLA_APB>,
				<&rstgen RSTN_NNENOC_AXI>,
				<&rstgen RSTN_DLASLV_AXI>;
			interrupts = <22>;
			memory-region = <&nvdla_reserved>;
			reg = <0x0 0x11940000 0x0 0x40000>;
			status = "okay";
		};

		jpu: coadj12@11900000 {
			compatible = "cm,codaj12-jpu-1";
			reg = <0x0 0x11900000 0x0 0x300>;
			memory-region = <&jpu_reserved>;
			interrupt-parent = <&plic>;
			interrupts = <24>;
			clocks = <&jpuclk>;
			clock-names = "jpege";
			reg-names = "control";
			resets = <&rstgen RSTN_JPEG_AXI>, <&rstgen RSTN_JPEG_CCLK>,
			       <&rstgen RSTN_JPEG_APB>;
			status = "okay";
		};

		clkgen: clock-controller@11800000 {
			compatible = "starfive,jh7100-clkgen";
			reg = <0x0 0x11800000 0x0 0x10000>;
			clocks = <&osc_sys>, <&osc_aud>;
			clock-names = "osc_sys", "osc_aud";
			#clock-cells = <1>;
		};

		vpu_dec: vpu_dec@118f0000 {
			compatible = "cm,cm511-vpu";
			reg = <0 0x118f0000 0 0x10000>;
			//memory-region = <&vpu_reserved>;
			interrupt-parent = <&plic>;
			interrupts = <23>;
			clocks = <&vpuclk>;
			clock-names = "vcodec";
			resets = <&rstgen RSTN_VDEC_AXI>, <&rstgen RSTN_VDECBRG_MAIN>,
			    <&rstgen RSTN_VDEC_BCLK>, <&rstgen RSTN_VDEC_CCLK>,
			    <&rstgen RSTN_VDEC_APB>;
			status = "okay";
		};

		vpu_enc: vpu_enc@118e0000 {
			compatible = "cm,cm521-vpu";
			reg = <0x0 0x118e0000 0x0 0x4000>;
			interrupt-parent = <&plic>;
			interrupts = <26>;
			clocks = <&vpuclk>;
			clock-names = "vcodec";
			resets = <&rstgen RSTN_VENC_AXI>, <&rstgen RSTN_VENCBRG_MAIN>,
			    <&rstgen RSTN_VENC_BCLK>, <&rstgen RSTN_VENC_CCLK>,
			    <&rstgen RSTN_VENC_APB>;
			reg-names = "control";
		};

		wdt: watchdogm@12480000 {
			compatible = "starfive,wdt";
			reg = <0x0 0x12480000 0x0 0x10000>;
			clocks = <&clkgen CLK_WDTIMER_APB>,<&clkgen CLK_WDT_CORE>;
			clock-names = "bus", "core";
			resets = <&rstgen RSTN_WDTIMER_APB>, <&rstgen RSTN_WDT>;
			reset-names = "bus", "core";
		};

		ptc: pwm@12490000 {
			compatible = "starfive,pwm0";
			reg = <0x0 0x12490000 0x0 0x10000>;
			reg-names = "control";
			sifive,approx-period = <100000000>;
			clocks = <&pwmclk>;
			#pwm-cells = <3>;
			sifive,npwm = <8>;

		};

		rstgen: reset-controller@11840000 {
			compatible = "starfive,jh7100-rstgen";
			reg = <0x0 0x11840000 0x0 0x10000>;
			#reset-cells = <1>;
		};

		spi2ahb {
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			compatible = "starfive,spi2ahb";
			resets = <&rstgen RSTN_SPI2AHB_AHB>, <&rstgen RSTN_SPI2AHB_CORE>;

			qspi: spi@11860000 {
				compatible = "cadence,qspi", "cdns,qspi-nor";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x0 0x11860000 0x0 0x10000 0x0 0x20000000 0x0 0x20000000>;
				interrupts = <3>;
				interrupt-parent = <&plic>;
				clocks = <&qspi_clk>;
				cdns,fifo-depth = <256>;
				cdns,fifo-width = <4>;
				cdns,trigger-address = <0x00000000>;
				status = "disabled";
				spi-max-frequency = <250000000>;
			};

			spi2: spi@12410000 {
				compatible = "snps,dw-apb-ssi";
				#address-cells = <1>;
				#size-cells = <0>;
				interrupt-parent = <&plic>;
				interrupts = <70>;
				reg = <0x0 0x12410000 0x0 0x10000>;
				clocks = <&spiclk>;
				status = "disabled";
				/*
				num-cs = <1>;
				cs-gpios = <&gpio 0 0>;
				*/
			};
		};

		xrp@f0000000 {
			compatible = "cdns,xrp";
			reg = <0x0  0xf0000000 0x0 0x01ffffff
			       0x10 0x72000000 0x0 0x00001000
			       0x10 0x72001000 0x0 0x00fff000
			       0x0  0x124b0000 0x0 0x00010000>;
			clocks = <&osc_sys>;
			interrupt-parent = <&plic>;
			firmware-name = "vp6_elf";
			resets = <&rstgen RSTN_VP6INTC_APB>;
			dsp-irq = <19 20>;
			dsp-irq-src = <0x20 0x21>;
			intc-irq-mode = <1>;
			intc-irq = <0 1>;
			interrupts = <27 28>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x40000000 0x0  0x40000000 0x01000000
			          0xb0000000 0x10 0x70000000 0x3000000>;
			dsp@0 {
			};
		};

		sdio0: sdio0@10000000 {
			compatible = "starfive,jh7100-dw-mshc", "snps,dw-mshc";
			reg = <0x0 0x10000000 0x0 0x10000>;
			interrupts = <4>;
			interrupt-parent = <&plic>;
			clocks = <&clkgen CLK_SDIO0_AHB>, <&clkgen CLK_SDIO0_CCLKINT>;
			clock-names = "biu", "ciu";
			resets = <&rstgen RSTN_SDIO0_AHB>;
			reset-names = "reset";
			clock-frequency = <100000000>;
			max-frequency = <10000000>;
			fifo-depth = <32>;
			card-detect-delay = <300>;
			fifo-watermark-aligned;
			data-addr = <0>;
			post-power-on-delay-ms = <200>;
			status = "disabled";
		};

		sdio1: sdio1@10010000 {
			compatible = "starfive,jh7100-dw-mshc", "snps,dw-mshc";
			reg = <0x0 0x10010000 0x0 0x10000>;
			interrupts = <5>;
			interrupt-parent = <&plic>;
			clocks = <&clkgen CLK_SDIO1_AHB>, <&clkgen CLK_SDIO1_CCLKINT>;
			clock-names = "biu", "ciu";
			resets = <&rstgen RSTN_SDIO1_AHB>;
			reset-names = "reset";
			clock-frequency = <100000000>;
			max-frequency = <10000000>;
			fifo-depth = <32>;
			card-detect-delay = <300>;
			fifo-watermark-aligned;
			data-addr = <0>;
			bus-width = <4>;
			cap-sd-highspeed;
			cap-sdio-irq;
			cap-mmc-hw-reset;
			enable-sdio-wakeup;
			keep-power-in-suspend;
			cap-mmc-highspeed;
			post-power-on-delay-ms = <200>;
			status = "disabled";
		};

		sfivefb: sfivefb@12000000 {
			compatible = "starfive,vpp-lcdc";
			interrupt-parent = <&plic>;
			interrupts = <101>, <103>;
			interrupt-names = "lcdc_irq", "vpp1_irq";
			reg = <0x0 0x12000000 0x0 0x10000>,
				<0x0 0x12100000 0x0 0x10000>,
				<0x0 0x12040000 0x0 0x10000>,
				<0x0 0x12080000 0x0 0x10000>,
				<0x0 0x120c0000 0x0 0x10000>,
				<0x0 0x12240000 0x0 0x10000>,
				<0x0 0x12250000 0x0 0x10000>,
				<0x0 0x12260000 0x0 0x10000>;
			reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
			memory-region = <&sffb_reserved>;
			clocks = <&uartclk>, <&apb2clk>;
			clock-names = "baudclk", "apb_pclk";
			status = "okay";
			ddr-format = <4>;/* LCDC win_format WIN_FMT_RGB565 */
		};

		vin_sysctl: vin_sysctl@19800000 {
			compatible = "starfive,stf-vin";
			reg = <0x0 0x19800000 0x0 0x10000>,
			      <0x0 0x19810000 0x0 0x10000>,
			      <0x0 0x19820000 0x0 0x10000>,
			      <0x0 0x19830000 0x0 0x10000>,
			      <0x0 0x19840000 0x0 0x10000>,
			      <0x0 0x19870000 0x0 0x30000>,
			      <0x0 0x198a0000 0x0 0x30000>,
			      <0x0 0x11800000 0x0 0x10000>,
			      <0x0 0x11840000 0x0 0x10000>,
			      <0x0 0x11858000 0x0 0x10000>;
			reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
			            "isp0", "isp1", "tclk", "trst", "iopad";
			interrupt-parent = <&plic>;
			interrupts = <119 109>;
			memory-region = <&vin_reserved>;
			/*defaule config for imx219 vin&isp*/
			format = <3>; /* SRC_CSI2RX_VIN_ISP */
			frame-width = <800>;
			frame-height =<480>;
			isp0_enable;
			csi-lane = <2>;
			csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>;
			csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>;
			csi-clane-swap = /bits/ 8 <0>;
			csi-clane-pn-swap = /bits/ 8 <0>;
			csi-mipiID = <0>;
			csi-width = <1920>;
			csi-height = <1080>;
			csi-dt = <0x2b>;
		};

		sfc_tmp: tmpsensor@124a0000 {
			compatible = "sfc,tempsensor";
			reg = <0x0 0x124a0000 0x0 0x1000>;
			interrupt-parent = <&plic>;
			interrupts = <122>;
			resets = <&rstgen RSTN_TEMP_APB>, <&rstgen RSTN_TEMP_SENSE>;
			status = "okay";
		};

		otp: otp@11810000 {
			compatible = "starfive,fu740-otp";
			reg = <0x0 0x11810000 0x0 0x10000>;
			fuse-count = <0x200>;
			resets = <&rstgen RSTN_OTP_APB>;
			clocks = <&clkgen CLK_OTP_APB>;
		};
	};
};