/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2016, STMicroelectronics - All Rights Reserved * Author(s): Vikas Manocha, for STMicroelectronics. */ #ifndef _SERIAL_STM32_ #define _SERIAL_STM32_ #define CR1_OFFSET(x) (x ? 0x0c : 0x00) #define CR3_OFFSET(x) (x ? 0x14 : 0x08) #define BRR_OFFSET(x) (x ? 0x08 : 0x0c) #define ISR_OFFSET(x) (x ? 0x00 : 0x1c) #define ICR_OFFSET 0x20 /* * STM32F4 has one Data Register (DR) for received or transmitted * data, so map Receive Data Register (RDR) and Transmit Data * Register (TDR) at the same offset */ #define RDR_OFFSET(x) (x ? 0x04 : 0x24) #define TDR_OFFSET(x) (x ? 0x04 : 0x28) #define USART_CR1_FIFOEN BIT(29) #define USART_CR1_M1 BIT(28) #define USART_CR1_OVER8 BIT(15) #define USART_CR1_M0 BIT(12) #define USART_CR1_PCE BIT(10) #define USART_CR1_PS BIT(9) #define USART_CR1_TE BIT(3) #define USART_CR1_RE BIT(2) #define USART_CR3_OVRDIS BIT(12) #define USART_ISR_TXE BIT(7) #define USART_ISR_RXNE BIT(5) #define USART_ISR_ORE BIT(3) #define USART_ISR_PE BIT(0) #define USART_BRR_F_MASK GENMASK(7, 0) #define USART_BRR_M_SHIFT 4 #define USART_BRR_M_MASK GENMASK(15, 4) #define USART_ICR_ORECF BIT(3) #define USART_ICR_PCECF BIT(0) #endif