* CoreSight Components: CoreSight components are compliant with the ARM CoreSight architecture specification and can be connected in various topologies to suit a particular SoCs tracing needs. These trace components can generally be classified as sinks, links and sources. Trace data produced by one or more sources flows through the intermediate links connecting the source to the currently selected sink. Each CoreSight component device should use these properties to describe its hardware characteristcs. * Required properties for all components *except* non-configurable replicators: * compatible: These have to be supplemented with "arm,primecell" as drivers are using the AMBA bus interface. Possible values include: - Embedded Trace Buffer (version 1.0): "arm,coresight-etb10", "arm,primecell"; - Trace Port Interface Unit: "arm,coresight-tpiu", "arm,primecell"; - Trace Memory Controller, used for Embedded Trace Buffer(ETB), Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configuration. The configuration mode (ETB, ETF, ETR) is discovered at boot time when the device is probed. "arm,coresight-tmc", "arm,primecell"; - Trace Funnel: "arm,coresight-funnel", "arm,primecell"; - Embedded Trace Macrocell (version 3.x) and Program Flow Trace Macrocell: "arm,coresight-etm3x", "arm,primecell"; - Embedded Trace Macrocell (version 4.x): "arm,coresight-etm4x", "arm,primecell"; - Qualcomm Configurable Replicator (version 1.x): "qcom,coresight-replicator1x", "arm,primecell"; - System Trace Macrocell: "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component. * clocks: the clocks associated to this component. * clock-names: the name of the clocks referenced by the code. Since we are using the AMBA framework, the name of the clock providing the interconnect should be "apb_pclk", and some coresight blocks also have an additional clock "atclk", which clocks the core of that coresight component. The latter clock is optional. * port or ports: The representation of the component's port layout using the generic DT graph presentation found in "bindings/graph.txt". * Additional required properties for System Trace Macrocells (STM): * reg: along with the physical base address and length of the register set as described above, another entry is required to describe the mapping of the extended stimulus port area. * reg-names: the only acceptable values are "stm-base" and "stm-stimulus-base", each corresponding to the areas defined in "reg". * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: * compatible: Currently supported value is (note the absence of the AMBA markee): - "arm,coresight-replicator" * port or ports: same as above. * Optional properties for ETM/PTMs: * arm,cp14: must be present if the system accesses ETM/PTM management registers via co-processor 14. * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the source is considered to belong to CPU0. * Optional property for TMC: * arm,buffer-size: size of contiguous buffer space for TMC ETR (embedded trace router) Example: 1. Sinks etb@20010000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0 0x20010000 0 0x1000>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; port { etb_in_port: endpoint@0 { slave-mode; remote-endpoint = <&replicator_out_port0>; }; }; }; tpiu@20030000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0 0x20030000 0 0x1000>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; port { tpiu_in_port: endpoint@0 { slave-mode; remote-endpoint = <&replicator_out_port1>; }; }; }; 2. Links replicator { /* non-configurable replicators don't show up on the * AMBA bus. As such no need to add "arm,primecell". */ compatible = "arm,coresight-replicator"; ports { #address-cells = <1>; #size-cells = <0>; /* replicator output ports */ port@0 { reg = <0>; replicator_out_port0: endpoint { remote-endpoint = <&etb_in_port>; }; }; port@1 { reg = <1>; replicator_out_port1: endpoint { remote-endpoint = <&tpiu_in_port>; }; }; /* replicator input port */ port@2 { reg = <0>; replicator_in_port0: endpoint { slave-mode; remote-endpoint = <&funnel_out_port0>; }; }; }; }; funnel@20040000 { compatible = "arm,coresight-funnel", "arm,primecell"; reg = <0 0x20040000 0 0x1000>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; ports { #address-cells = <1>; #size-cells = <0>; /* funnel output port */ port@0 { reg = <0>; funnel_out_port0: endpoint { remote-endpoint = <&replicator_in_port0>; }; }; /* funnel input ports */ port@1 { reg = <0>; funnel_in_port0: endpoint { slave-mode; remote-endpoint = <&ptm0_out_port>; }; }; port@2 { reg = <1>; funnel_in_port1: endpoint { slave-mode; remote-endpoint = <&ptm1_out_port>; }; }; port@3 { reg = <2>; funnel_in_port2: endpoint { slave-mode; remote-endpoint = <&etm0_out_port>; }; }; }; }; 3. Sources ptm@2201c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0 0x2201c000 0 0x1000>; cpu = <&cpu0>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; port { ptm0_out_port: endpoint { remote-endpoint = <&funnel_in_port0>; }; }; }; ptm@2201d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0 0x2201d000 0 0x1000>; cpu = <&cpu1>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; port { ptm1_out_port: endpoint { remote-endpoint = <&funnel_in_port1>; }; }; }; 4. STM stm@20100000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x20100000 0 0x1000>, <0 0x28000000 0 0x180000>; reg-names = "stm-base", "stm-stimulus-base"; clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; port { stm_out_port: endpoint { remote-endpoint = <&main_funnel_in_port2>; }; }; }; [1]. There is currently two version of STM: STM32 and STM500. Both have the same HW interface and as such don't need an explicit binding name.