* ARM L2 Cache Controller ARM cores often have a separate level 2 cache controller. There are various implementations of the L2 cache controller with compatible programming models. Some of the properties that are just prefixed "cache-*" are taken from section 3.7.3 of the ePAPR v1.1 specification which can be found at: https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf The ARM L2 cache representation in the device tree should be done as follows: Required properties: - compatible : should be one of: "arm,pl310-cache" "arm,l220-cache" "arm,l210-cache" "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache" "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an offset needs to be added to the address before passing down to the L2 cache controller "marvell,aurora-system-cache": Marvell Controller designed to be compatible with the ARM one, with system cache mode (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation). "marvell,aurora-outer-cache": Marvell Controller designed to be compatible with the ARM one with outer cache mode. "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible with arm,pl310-cache controller. - cache-unified : Specifies the cache is a unified cache. - cache-level : Should be set to 2 for a level 2 cache. - reg : Physical base address and size of cache controller's memory mapped registers. Optional properties: - arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of read, write and setup latencies. Minimum valid values are 1. Controllers without setup latency control should use a value of 0. - arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of read, write and setup latencies. Controllers without setup latency control should use 0. Controllers without separate read and write Tag RAM latency values should only use the first cell. - arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. - arm,filter-ranges : Starting address and length of window to filter. Addresses in the filter window are directed to the M1 port. Other addresses will go to the M0 port. - arm,io-coherent : indicates that the system is operating in an hardware I/O coherent mode. Valid only when the arm,pl310-cache compatible string is used. - interrupts : 1 combined interrupt. - cache-size : specifies the size in bytes of the cache - cache-sets : specifies the number of associativity sets of the cache - cache-block-size : specifies the size in bytes of a cache block - cache-line-size : specifies the size in bytes of a line in the cache, if this is not specified, the line size is assumed to be equal to the cache block size - cache-id-part: cache id part number to be used if it is not present on hardware - wt-override: If present then L2 is forced to Write through mode - arm,double-linefill : Override double linefill enable setting. Enable if non-zero, disable if zero. - arm,double-linefill-incr : Override double linefill on INCR read. Enable if non-zero, disable if zero. - arm,double-linefill-wrap : Override double linefill on WRAP read. Enable if non-zero, disable if zero. - arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero, disable if zero. - arm,prefetch-offset : Override prefetch offset value. Valid values are 0-7, 15, 23, and 31. Example: L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xfff12000 0x1000>; arm,data-latency = <1 1 1>; arm,tag-latency = <2 2 2>; arm,filter-ranges = <0x80000000 0x8000000>; cache-unified; cache-level = <2>; interrupts = <45>; };