Device tree bindings for i.MX Wireless External Interface Module (WEIM) The term "wireless" does not imply that the WEIM is literally an interface without wires. It simply means that this module was originally designed for wireless and mobile applications that use low-power technology. The actual devices are instantiated from the child nodes of a WEIM node. Required properties: - compatible: Should contain one of the following: "fsl,imx1-weim" "fsl,imx27-weim" "fsl,imx51-weim" "fsl,imx50-weim" "fsl,imx6q-weim" - reg: A resource specifier for the register space (see the example below) - clocks: the clock, see the example below. - #address-cells: Must be set to 2 to allow memory address translation - #size-cells: Must be set to 1 to allow CS address passing - ranges: Must be set up to reflect the memory layout with four integer values for each chip-select line in use: 0 Optional properties: - fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of devices, it should be the phandle to the system General Purpose Register controller that contains WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0] should be set up as one of the following 4 possible values depending on the CS space configuration. IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3 --------------------------------------------- 05 128M 0M 0M 0M 033 64M 64M 0M 0M 0113 64M 32M 32M 0M 01111 32M 32M 32M 32M In case that the property is absent, the reset value or what bootloader sets up in IOMUXC_GPR1[11:0] will be used. - fsl,burst-clk-enable For "fsl,imx50-weim" and "fsl,imx6q-weim" type of devices, the presence of this property indicates that the weim bus should operate in Burst Clock Mode. - fsl,continuous-burst-clk Make Burst Clock to output continuous clock. Without this option Burst Clock will output clock only when necessary. This takes effect only if "fsl,burst-clk-enable" is set. Timing property for child nodes. It is mandatory, not optional. - fsl,weim-cs-timing: The timing array, contains timing values for the child node. We get the CS indexes from the address ranges in the child node's "reg" property. The number of registers depends on the selected chip: For i.MX1, i.MX21 ("fsl,imx1-weim") there are two registers: CSxU, CSxL. For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim") there are three registers: CSCRxU, CSCRxL, CSCRxA. For i.MX50, i.MX53 ("fsl,imx50-weim"), i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim") there are six registers: CSxGCR1, CSxGCR2, CSxRCR1, CSxRCR2, CSxWCR1, CSxWCR2. Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM: weim: weim@21b8000 { compatible = "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; clocks = <&clks 196>; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0x08000000 0x08000000>; fsl,weim-cs-gpr = <&gpr>; nor@0,0 { compatible = "cfi-flash"; reg = <0 0 0x02000000>; #address-cells = <1>; #size-cells = <1>; bank-width = <2>; fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 0x0000c000 0x1404a38e 0x00000000>; }; }; Example for an imx6q-based board, a multi-chipselect device connected to WEIM: In this case, both chip select 0 and 1 will be configured with the same timing array values. weim: weim@21b8000 { compatible = "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; clocks = <&clks 196>; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0x08000000 0x02000000 1 0 0x0a000000 0x02000000 2 0 0x0c000000 0x02000000 3 0 0x0e000000 0x02000000>; fsl,weim-cs-gpr = <&gpr>; acme@0 { compatible = "acme,whatever"; reg = <0 0 0x100>, <0 0x400000 0x800>, <1 0x400000 0x800>; fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100 0x00000000 0xa0000240 0x00000000>; }; };