* Renesas R8A73A4 Clock Pulse Generator (CPG) The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs and several fixed ratio dividers. Required Properties: - compatible: Must be "renesas,r8a73a4-cpg-clocks" - reg: Base address and length of the memory resource used by the CPG - clocks: Reference to the parent clocks ("extal1" and "extal2") - #clock-cells: Must be 1 - clock-output-names: The names of the clocks. Supported clocks are "main", "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", "m1", "m2", "zx", "zs", and "hp". Example ------- cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a73a4-cpg-clocks"; reg = <0 0xe6150000 0 0x10000>; clocks = <&extal1_clk>, <&extal2_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", "m1", "m2", "zx", "zs", "hp"; };