Allwinner Display Engine 2.0/3.0 Clock Control Binding
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Required properties :
- compatible: must contain one of the following compatibles:
		- "allwinner,sun8i-a83t-de2-clk"
		- "allwinner,sun8i-h3-de2-clk"
		- "allwinner,sun8i-v3s-de2-clk"
		- "allwinner,sun50i-a64-de2-clk"
		- "allwinner,sun50i-h5-de2-clk"
		- "allwinner,sun50i-h6-de3-clk"

- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the display engine subsystem.
	  Three are needed:
  - "mod": the display engine module clock (on A83T it's the DE PLL)
  - "bus": the bus clock for the whole display engine subsystem
- clock-names: Must contain the clock names described just above
- resets: phandle to the reset control for the display engine subsystem.
- #clock-cells : must contain 1
- #reset-cells : must contain 1

Example:
de2_clocks: clock@1000000 {
	compatible = "allwinner,sun8i-h3-de2-clk";
	reg = <0x01000000 0x100000>;
	clocks = <&ccu CLK_BUS_DE>,
		 <&ccu CLK_DE>;
	clock-names = "bus",
		      "mod";
	resets = <&ccu RST_BUS_DE>;
	#clock-cells = <1>;
	#reset-cells = <1>;
};