# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MSM Display Port Controller maintainers: - Kuogee Hsieh description: | Device tree bindings for DisplayPort host controller for MSM targets that are compatible with VESA DisplayPort interface specification. properties: compatible: enum: - qcom,sc7180-dp reg: maxItems: 1 interrupts: maxItems: 1 clocks: items: - description: AHB clock to enable register access - description: Display Port AUX clock - description: Display Port Link clock - description: Link interface clock between DP and PHY - description: Display Port Pixel clock clock-names: items: - const: core_iface - const: core_aux - const: ctrl_link - const: ctrl_link_iface - const: stream_pixel assigned-clocks: items: - description: link clock source - description: pixel clock source assigned-clock-parents: items: - description: phy 0 parent - description: phy 1 parent phys: maxItems: 1 phy-names: items: - const: dp operating-points-v2: maxItems: 1 power-domains: maxItems: 1 "#sound-dai-cells": const: 0 ports: $ref: /schemas/graph.yaml#/properties/ports properties: port@0: $ref: /schemas/graph.yaml#/properties/port description: Input endpoint of the controller port@1: $ref: /schemas/graph.yaml#/properties/port description: Output endpoint of the controller required: - compatible - reg - interrupts - clocks - clock-names - phys - phy-names - "#sound-dai-cells" - power-domains - ports additionalProperties: false examples: - | #include #include #include #include displayport-controller@ae90000 { compatible = "qcom,sc7180-dp"; reg = <0xae90000 0x1400>; interrupt-parent = <&mdss>; interrupts = <12>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; phys = <&dp_phy>; phy-names = "dp"; #sound-dai-cells = <0>; power-domains = <&rpmhpd SC7180_CX>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; endpoint { remote-endpoint = <&dpu_intf0_out>; }; }; port@1 { reg = <1>; endpoint { remote-endpoint = <&typec>; }; }; }; }; ...