NXP Layerscape SoC qDMA Controller ================================== This device follows the generic DMA bindings defined in dma/dma.txt. Required properties: - compatible: Must be one of "fsl,ls1021a-qdma": for LS1021A Board "fsl,ls1043a-qdma": for ls1043A Board "fsl,ls1046a-qdma": for ls1046A Board - reg: Should contain the register's base address and length. - interrupts: Should contain a reference to the interrupt used by this device. - interrupt-names: Should contain interrupt names: "qdma-queue0": the block0 interrupt "qdma-queue1": the block1 interrupt "qdma-queue2": the block2 interrupt "qdma-queue3": the block3 interrupt "qdma-error": the error interrupt - fsl,dma-queues: Should contain number of queues supported. - dma-channels: Number of DMA channels supported - block-number: the virtual block number - block-offset: the offset of different virtual block - status-sizes: status queue size of per virtual block - queue-sizes: command queue size of per virtual block, the size number based on queues Optional properties: - dma-channels: Number of DMA channels supported by the controller. - big-endian: If present registers and hardware scatter/gather descriptors of the qDMA are implemented in big endian mode, otherwise in little mode. Examples: qdma: dma-controller@8390000 { compatible = "fsl,ls1021a-qdma"; reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ <0x0 0x8389000 0x0 0x1000>, /* Status regs */ <0x0 0x838a000 0x0 0x2000>; /* Block regs */ interrupts = , , ; interrupt-names = "qdma-error", "qdma-queue0", "qdma-queue1"; dma-channels = <8>; block-number = <2>; block-offset = <0x1000>; fsl,dma-queues = <2>; status-sizes = <64>; queue-sizes = <64 64>; big-endian; }; DMA clients must use the format described in dma/dma.txt file.