I2C for Atmel platforms Required properties : - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c", "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c", "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c" - reg: physical base address of the controller and length of memory mapped region. - interrupts: interrupt number to the cpu. - #address-cells = <1>; - #size-cells = <0>; - clocks: phandles to input clocks. Optional properties: - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 - dmas: A list of two dma specifiers, one for each entry in dma-names. - dma-names: should contain "tx" and "rx". - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO capable I2C controllers. - i2c-sda-hold-time-ns: TWD hold time, only available for "atmel,sama5d4-i2c" and "atmel,sama5d2-i2c". - Child nodes conforming to i2c bus binding Examples : i2c0: i2c@fff84000 { compatible = "atmel,at91sam9g20-i2c"; reg = <0xfff84000 0x100>; interrupts = <12 4 6>; #address-cells = <1>; #size-cells = <0>; clocks = <&twi0_clk>; clock-frequency = <400000>; 24c512@50 { compatible = "24c512"; reg = <0x50>; pagesize = <128>; } } i2c0: i2c@f8034600 { compatible = "atmel,sama5d2-i2c"; reg = <0xf8034600 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) AT91_XDMAC_DT_PERID(11)>, <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) AT91_XDMAC_DT_PERID(12)>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; clocks = <&flx0>; atmel,fifo-size = <16>; i2c-sda-hold-time-ns = <336>; wm8731: wm8731@1a { compatible = "wm8731"; reg = <0x1a>; }; };