Broadcom BCM6345-style Level 1 interrupt controller This block is a first level interrupt controller that is typically connected directly to one of the HW INT lines on each CPU. Key elements of the hardware design include: - 32, 64 or 128 incoming level IRQ lines - Most onchip peripherals are wired directly to an L1 input - A separate instance of the register set for each CPU, allowing individual peripheral IRQs to be routed to any CPU - Contains one or more enable/status word pairs per CPU - No atomic set/clear operations - No polarity/level/edge settings - No FIFO or priority encoder logic; software is expected to read all 2-4 status words to determine which IRQs are pending Required properties: - compatible: should be "brcm,bcm-l1-intc", "brcm,bcm6345-l1-intc" - reg: specifies the base physical address and size of the registers; the number of supported IRQs is inferred from the size argument - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: specifies the number of cells needed to encode an interrupt source, should be 1. - interrupt-parent: specifies the phandle to the parent interrupt controller(s) this one is cascaded from - interrupts: specifies the interrupt line(s) in the interrupt-parent controller node; valid values depend on the type of parent interrupt controller If multiple reg ranges and interrupt-parent entries are present on an SMP system, the driver will allow IRQ SMP affinity to be set up through the /proc/irq/ interface. In the simplest possible configuration, only one reg range and one interrupt-parent is needed. The driver operates in native CPU endian by default, there is no support for specifying an alternative endianness. Example: periph_intc: interrupt-controller@10000000 { compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc"; reg = <0x10000020 0x20>, <0x10000040 0x20>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&cpu_intc>; interrupts = <2>, <3>; };