Marvell SEI (System Error Interrupt) Controller ----------------------------------------------- Marvell SEI (System Error Interrupt) controller is an interrupt aggregator. It receives interrupts from several sources and aggregates them to a single interrupt line (an SPI) on the parent interrupt controller. This interrupt controller can handle up to 64 SEIs, a set comes from the AP and is wired while a second set comes from the CPs by the mean of MSIs. Required properties: - compatible: should be one of: * "marvell,ap806-sei" - reg: SEI registers location and length. - interrupts: identifies the parent IRQ that will be triggered. - #interrupt-cells: number of cells to define an SEI wired interrupt coming from the AP, should be 1. The cell is the IRQ number. - interrupt-controller: identifies the node as an interrupt controller for AP interrupts. - msi-controller: identifies the node as an MSI controller for the CPs interrupts. Example: sei: interrupt-controller@3f0200 { compatible = "marvell,ap806-sei"; reg = <0x3f0200 0x40>; interrupts = ; #interrupt-cells = <1>; interrupt-controller; msi-controller; };