* Mediatek JPEG Decoder Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs Required properties: - compatible : must be one of the following string: "mediatek,mt8173-jpgdec" "mediatek,mt2701-jpgdec" - reg : physical base address of the jpeg decoder registers and length of memory mapped region. - interrupts : interrupt number to the interrupt controller. - clocks: device clocks, see Documentation/devicetree/bindings/clock/clock-bindings.txt for details. - clock-names: must contain "jpgdec-smi" and "jpgdec". - power-domains: a phandle to the power domain, see Documentation/devicetree/bindings/power/power_domain.txt for details. - mediatek,larb: must contain the local arbiters in the current Socs, see Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt for details. - iommus: should point to the respective IOMMU block with master port as argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt for details. Example: jpegdec: jpegdec@15004000 { compatible = "mediatek,mt2701-jpgdec"; reg = <0 0x15004000 0 0x1000>; interrupts = ; clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, <&imgsys CLK_IMG_JPGDEC>; clock-names = "jpgdec-smi", "jpgdec"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; mediatek,larb = <&larb2>; iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; };