# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/media/samsung,fimc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung S5P/Exynos SoC Camera Subsystem (FIMC) maintainers: - Krzysztof Kozlowski - Sylwester Nawrocki description: | The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices represented by separate device tree nodes. Currently this includes: Fully Integrated Mobile Camera (FIMC, in the S5P SoCs series known as CAMIF), MIPI CSIS, FIMC-LITE and FIMC-IS (ISP). properties: compatible: const: samsung,fimc ranges: true '#address-cells': const: 1 '#size-cells': const: 1 '#clock-cells': const: 1 description: | The clock specifier cell stores an index of a clock: 0, 1 for CAM_A_CLKOUT, CAM_B_CLKOUT clocks respectively. clocks: minItems: 2 maxItems: 4 clock-names: minItems: 2 items: - const: sclk_cam0 - const: sclk_cam1 - const: pxl_async0 - const: pxl_async1 clock-output-names: maxItems: 2 parallel-ports: $ref: /schemas/graph.yaml#/properties/ports description: Active parallel video input ports. patternProperties: "^port@[01]$": $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: Camera A and camera B inputs. properties: endpoint: $ref: /schemas/media/video-interfaces.yaml# unevaluatedProperties: false pinctrl-names: minItems: 1 items: - const: default - const: idle - const: active_a - const: active_b patternProperties: "^csis@[0-9a-f]+$": type: object $ref: samsung,exynos4210-csis.yaml# description: MIPI CSI-2 receiver. "^fimc@[0-9a-f]+$": type: object $ref: samsung,exynos4210-fimc.yaml# description: Fully Integrated Mobile Camera. "^fimc-is@[0-9a-f]+$": type: object $ref: samsung,exynos4212-fimc-is.yaml# description: Imaging Subsystem (FIMC-IS). "^fimc-lite@[0-9a-f]+$": type: object $ref: samsung,exynos4212-fimc-lite.yaml# description: Camera host interface (FIMC-LITE). required: - compatible - '#address-cells' - '#clock-cells' - clocks - clock-names - clock-output-names - ranges - '#size-cells' additionalProperties: false examples: - | #include #include #include camera@11800000 { compatible = "samsung,fimc"; #clock-cells = <1>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0xba1000>; clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; clock-output-names = "cam_a_clkout", "cam_b_clkout"; assigned-clocks = <&clock CLK_MOUT_CAM0>, <&clock CLK_MOUT_CAM1>; assigned-clock-parents = <&clock CLK_XUSBXTI>, <&clock CLK_XUSBXTI>; pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; pinctrl-names = "default"; fimc@0 { compatible = "samsung,exynos4212-fimc"; reg = <0x00000000 0x1000>; interrupts = ; clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; clock-names = "fimc", "sclk_fimc"; power-domains = <&pd_cam>; samsung,sysreg = <&sys_reg>; iommus = <&sysmmu_fimc0>; samsung,pix-limits = <4224 8192 1920 4224>; samsung,mainscaler-ext; samsung,isp-wb; samsung,cam-if; }; /* ... FIMC 1-3 */ csis@80000 { compatible = "samsung,exynos4210-csis"; reg = <0x00080000 0x4000>; interrupts = ; clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; clock-names = "csis", "sclk_csis"; assigned-clocks = <&clock CLK_MOUT_CSIS0>, <&clock CLK_SCLK_CSIS0>; assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; assigned-clock-rates = <0>, <176000000>; bus-width = <4>; power-domains = <&pd_cam>; phys = <&mipi_phy 0>; phy-names = "csis"; #address-cells = <1>; #size-cells = <0>; vddcore-supply = <&ldo8_reg>; vddio-supply = <&ldo10_reg>; /* Camera C (3) MIPI CSI-2 (CSIS0) */ port@3 { reg = <3>; endpoint { remote-endpoint = <&s5c73m3_ep>; data-lanes = <1 2 3 4>; samsung,csis-hs-settle = <12>; }; }; }; /* ... CSIS 1 */ fimc-lite@b90000 { compatible = "samsung,exynos4212-fimc-lite"; reg = <0xb90000 0x1000>; interrupts = ; power-domains = <&pd_isp>; clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; clock-names = "flite"; iommus = <&sysmmu_fimc_lite0>; }; /* ... FIMC-LITE 1 */ fimc-is@800000 { compatible = "samsung,exynos4212-fimc-is"; reg = <0x00800000 0x260000>; interrupts = , ; clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, <&isp_clock CLK_ISP_FIMC_LITE1>, <&isp_clock CLK_ISP_PPMUISPX>, <&isp_clock CLK_ISP_PPMUISPMX>, <&isp_clock CLK_ISP_FIMC_ISP>, <&isp_clock CLK_ISP_FIMC_DRC>, <&isp_clock CLK_ISP_FIMC_FD>, <&isp_clock CLK_ISP_MCUISP>, <&isp_clock CLK_ISP_GICISP>, <&isp_clock CLK_ISP_MCUCTL_ISP>, <&isp_clock CLK_ISP_PWM_ISP>, <&isp_clock CLK_ISP_DIV_ISP0>, <&isp_clock CLK_ISP_DIV_ISP1>, <&isp_clock CLK_ISP_DIV_MCUISP0>, <&isp_clock CLK_ISP_DIV_MCUISP1>, <&clock CLK_MOUT_MPLL_USER_T>, <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>, <&clock CLK_DIV_ACLK200>, <&clock CLK_DIV_ACLK400_MCUISP>, <&clock CLK_UART_ISP_SCLK>; clock-names = "lite0", "lite1", "ppmuispx", "ppmuispmx", "isp", "drc", "fd", "mcuisp", "gicisp", "mcuctl_isp", "pwm_isp", "ispdiv0", "ispdiv1", "mcuispdiv0", "mcuispdiv1", "mpll", "aclk200", "aclk400mcuisp", "div_aclk200", "div_aclk400mcuisp", "uart"; iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; iommu-names = "isp", "drc", "fd", "mcuctl"; power-domains = <&pd_isp>; samsung,pmu-syscon = <&pmu_system_controller>; #address-cells = <1>; #size-cells = <1>; ranges; i2c-isp@940000 { compatible = "samsung,exynos4212-i2c-isp"; reg = <0x00940000 0x100>; clocks = <&isp_clock CLK_ISP_I2C1_ISP>; clock-names = "i2c_isp"; pinctrl-0 = <&fimc_is_i2c1>; pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; image-sensor@10 { compatible = "samsung,s5k6a3"; reg = <0x10>; svdda-supply = <&cam_io_reg>; svddio-supply = <&ldo19_reg>; afvdd-supply = <&ldo19_reg>; clock-frequency = <24000000>; /* CAM_B_CLKOUT */ clocks = <&camera 1>; clock-names = "extclk"; gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; port { endpoint { remote-endpoint = <&csis1_ep>; data-lanes = <1>; }; }; }; }; }; };