* Samsung Exynos specific extensions to the Synopsys Designware Mobile Storage Host Controller The Synopsys designware mobile storage host controller is used to interface a SoC with storage medium such as eMMC or SD/MMC cards. This file documents differences between the core Synopsys dw mshc controller properties described by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific extensions to the Synopsys Designware Mobile Storage Host Controller. Required Properties: * compatible: should be - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210 specific extensions. - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412 specific extensions. - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 specific extensions. - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420 specific extensions. - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7 specific extensions. - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 specific extensions having an SMU. * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface unit (ciu) clock. This property is applicable only for Exynos5 SoC's and ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7. * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value in transmit mode and CIU clock phase shift value in receive mode for single data rate mode operation. Refer notes below for the order of the cells and the valid values. * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value in transmit mode and CIU clock phase shift value in receive mode for double data rate mode operation. Refer notes below for the order of the cells and the valid values. * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase shift value for hs400 mode operation. Notes for the sdr-timing and ddr-timing values: The order of the cells should be - First Cell: CIU clock phase shift value for tx mode. - Second Cell: CIU clock phase shift value for rx mode. Valid values for SDR and DDR CIU clock timing for Exynos5250: - valid value for tx phase shift and rx phase shift is 0 to 7. - when CIU clock divider value is set to 3, all possible 8 phase shift values can be used. - if CIU clock divider value is 0 (that is divide by 1), both tx and rx phase shift clocks should be 0. * samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode (Latency value for delay line in Read path) Required properties for a slot (Deprecated - Recommend to use one slot per host): * gpios: specifies a list of gpios used for command, clock and data bus. The first gpio is the command line and the second gpio is the clock line. The rest of the gpios (depending on the bus-width property) are the data lines in no particular order. The format of the gpio specifier depends on the gpio controller. (Deprecated - Refer to Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt) Example: The MSHC controller node can be split into two portions, SoC specific and board specific portions as listed below. dwmmc0@12200000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; interrupts = <0 75 0>; #address-cells = <1>; #size-cells = <0>; }; dwmmc0@12200000 { cap-mmc-highspeed; cap-sd-highspeed; broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; samsung,dw-mshc-hs400-timing = <0 2>; samsung,read-strobe-delay = <90>; bus-width = <8>; };