NXP LPC32xx SoC NAND MLC controller Required properties: - compatible: "nxp,lpc3220-mlc" - reg: Address and size of the controller - interrupts: The NAND interrupt specification - gpios: GPIO specification for NAND write protect The following required properties are very controller specific. See the LPC32xx User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in Hz, to make them independent of actual clock speed and to provide for good accuracy:) - nxp,tcea_delay: TCEA_DELAY - nxp,busy_delay: BUSY_DELAY - nxp,nand_ta: NAND_TA - nxp,rd_high: RD_HIGH - nxp,rd_low: RD_LOW - nxp,wr_high: WR_HIGH - nxp,wr_low: WR_LOW Optional subnodes: - Partitions, see Documentation/devicetree/bindings/mtd/partition.txt Example: mlc: flash@200a8000 { compatible = "nxp,lpc3220-mlc"; reg = <0x200A8000 0x11000>; interrupts = <11 0>; #address-cells = <1>; #size-cells = <1>; nxp,tcea-delay = <333333333>; nxp,busy-delay = <10000000>; nxp,nand-ta = <18181818>; nxp,rd-high = <31250000>; nxp,rd-low = <45454545>; nxp,wr-high = <40000000>; nxp,wr-low = <83333333>; gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ mtd0@00000000 { label = "boot"; reg = <0x00000000 0x00064000>; read-only; }; ... };