* Broadcom Starfighter 2 integrated swich Required properties: - compatible: should be "brcm,bcm7445-switch-v4.0" - reg: addresses and length of the register sets for the device, must be 6 pairs of register addresses and lengths - interrupts: interrupts for the devices, must be two interrupts - dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt - dsa,ethernet: phandle to the CPU network interface controller, see dsa/dsa.txt - #size-cells: must be 0 - #address-cells: must be 2, see dsa/dsa.txt Subnodes: The integrated switch subnode should be specified according to the binding described in dsa/dsa.txt. Optional properties: - reg-names: litteral names for the device base register addresses, when present must be: "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" - interrupt-names: litternal names for the device interrupt lines, when present must be: "switch_0" and "switch_1" - brcm,num-gphy: specify the maximum number of integrated gigabit PHYs in the switch - brcm,num-rgmii-ports: specify the maximum number of RGMII interfaces supported by the switch - brcm,fcb-pause-override: boolean property, if present indicates that the switch supports Failover Control Block pause override capability - brcm,acb-packets-inflight: boolean property, if present indicates that the switch Admission Control Block supports reporting the number of packets in-flight in a switch queue Example: switch_top@f0b00000 { compatible = "simple-bus"; #size-cells = <1>; #address-cells = <1>; ranges = <0 0xf0b00000 0x40804>; ethernet_switch@0 { compatible = "brcm,bcm7445-switch-v4.0"; #size-cells = <0>; #address-cells = <2>; reg = <0x0 0x40000 0x40000 0x110 0x40340 0x30 0x40380 0x30 0x40400 0x34 0x40600 0x208>; interrupts = <0 0x18 0 0 0x19 0>; brcm,num-gphy = <1>; brcm,num-rgmii-ports = <2>; brcm,fcb-pause-override; brcm,acb-packets-inflight; ... switch@0 { reg = <0 0>; #size-cells = <0>; #address-cells <1>; port@0 { label = "gphy"; reg = <0>; }; ... }; }; };