* Texas Instruments - dp83867 Giga bit ethernet phy Required properties: - reg - The ID number for the phy, usually a small integer - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h for applicable values. Required only if interface type is PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h for applicable values. Required only if interface type is PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable values Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock delays will be left at their default values, as set by the PHY's pin strapping. The default strapping will use a delay of 2.00 ns. Thus PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no internal delay, but as PHY_INTERFACE_MODE_RGMII_ID. The device tree should use "rgmii-id" if internal delays are desired as this may be changed in future to cause "rgmii" mode to disable delays. Optional property: - ti,min-output-impedance - MAC Interface Impedance control to set the programmable output impedance to minimum value (35 ohms). - ti,max-output-impedance - MAC Interface Impedance control to set the programmable output impedance to maximum value (70 ohms). - ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the board has RX_DV/RX_CTRL pin strapped in mode 1 or 2. To ensure PHY operation, there are specific actions that software needs to take when this pin is strapped in these modes. See data manual for details. - ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h for applicable values. The CLK_OUT pin can also be disabled by this property. When omitted, the PHY's default will be left as is. - ti,sgmii-ref-clock-output-enable - This denotes which SGMII configuration is used (4 or 6-wire modes). Some MACs work with differential SGMII clock. See data manual for details. Note: ti,min-output-impedance and ti,max-output-impedance are mutually exclusive. When both properties are present ti,max-output-impedance takes precedence. Default child nodes are standard Ethernet PHY device nodes as described in Documentation/devicetree/bindings/net/phy.txt Example: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; }; Datasheet can be found: http://www.ti.com/product/DP83867IR/datasheet