* Samsung Exynos 5440 PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. Required properties: - compatible: "samsung,exynos5440-pcie" - reg: base addresses and lengths of the PCIe controller, - reg-names : First name should be set to "elbi". And use the "config" instead of getting the configuration address space from "ranges". NOTE: When using the "config" property, reg-names must be set. - interrupts: A list of interrupt outputs for level interrupt, pulse interrupt, special interrupt. - phys: From PHY binding. Phandle for the generic PHY. Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt For other common properties, refer to Documentation/devicetree/bindings/pci/designware-pcie.txt Example: SoC-specific DT Entry (with using PHY framework): pcie_phy0: pcie-phy@270000 { ... reg = <0x270000 0x1000>, <0x271000 0x40>; reg-names = "phy", "block"; ... }; pcie@290000 { compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; reg = <0x290000 0x1000>, <0x40000000 0x1000>; reg-names = "elbi", "config"; clocks = <&clock 28>, <&clock 27>; clock-names = "pcie", "pcie_bus"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; phys = <&pcie_phy0>; ranges = <0x81000000 0 0 0x60001000 0 0x00010000 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; num-lanes = <4>; }; Board-specific DT Entry: pcie@290000 { reset-gpio = <&pin_ctrl 5 0>; }; pcie@2a0000 { reset-gpio = <&pin_ctrl 22 0>; };