# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: StarFive JH7100 Pin Controller description: | Bindings for the JH7100 RISC-V SoC from StarFive Ltd. Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63] and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have configurable bias, drive strength, schmitt trigger etc. The SoC has an interesting 2-layered approach to pin muxing best illustrated by the diagram below. Signal group 0, 1, ... or 6 ___|___ | | LCD output -----------------| | CMOS Camera interface ------| |--- PAD_GPIO[0] Ethernet PHY interface -----| MUX |--- PAD_GPIO[1] ... | | ... | |--- PAD_GPIO[63] -------- GPIO0 ------------| | | -------|-- GPIO1 --------| |--- PAD_FUNC_SHARE[0] | | | | | |--- PAD_FUNC_SHARE[1] | | | | ... | | ... | | | | | |--- PAD_FUNC_SHARE[141] | | -----|---|-- GPIO63 ---| | | | | | | | ------- UART0 UART1 -- The big MUX in the diagram only has 7 different ways of mapping peripherals on the left to pins on the right. StarFive calls the 7 configurations "signal groups". However some peripherals have their I/O go through the 64 "GPIOs". The diagram only shows UART0 and UART1, but this also includes a number of other UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64 GPIOs such that any GPIO can be set up to be controlled by any of the peripherals. Note that signal group 0 doesn't map any of the GPIOs to pins, and only signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63]. maintainers: - Emil Renner Berthing - Drew Fustini properties: compatible: const: starfive,jh7100-pinctrl reg: minItems: 2 maxItems: 2 reg-names: items: - const: gpio - const: padctl clocks: maxItems: 1 resets: maxItems: 1 gpio-controller: true "#gpio-cells": const: 2 interrupts: maxItems: 1 description: The GPIO parent interrupt. interrupt-controller: true "#interrupt-cells": const: 2 starfive,signal-group: description: | Select one of the 7 signal groups. If this property is not set it defaults to the configuration already chosen by the earlier boot stages. $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3, 4, 5, 6] required: - compatible - reg - reg-names - clocks - gpio-controller - "#gpio-cells" - interrupts - interrupt-controller - "#interrupt-cells" patternProperties: '-[0-9]+$': type: object patternProperties: '-pins$': type: object description: | A pinctrl node should contain at least one subnode representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer configuration, bias, input enable/disable, input schmitt trigger enable/disable, slew-rate and drive strength. $ref: /schemas/pinctrl/pincfg-node.yaml properties: pins: description: | The list of pin identifiers that properties in the node apply to. This should be set using either the PAD_GPIO or PAD_FUNC_SHARE macros. Either this or "pinmux" has to be specified, but not both. $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pins pinmux: description: | The list of GPIOs and their mux settings that properties in the node apply to. This should be set using the GPIOMUX macro. Either this or "pins" has to be specified, but not both. $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pinmux bias-disable: true bias-pull-up: type: boolean bias-pull-down: type: boolean drive-strength: enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ] input-enable: true input-disable: true input-schmitt-enable: true input-schmitt-disable: true slew-rate: maximum: 7 starfive,strong-pull-up: description: enable strong pull-up. type: boolean additionalProperties: false additionalProperties: false additionalProperties: false examples: - | #include #include #include soc { #address-cells = <2>; #size-cells = <2>; pinctrl@11910000 { compatible = "starfive,jh7100-pinctrl"; reg = <0x0 0x11910000 0x0 0x10000>, <0x0 0x11858000 0x0 0x1000>; reg-names = "gpio", "padctl"; clocks = <&clkgen JH7100_CLK_GPIO_APB>; resets = <&clkgen JH7100_RSTN_GPIO_APB>; interrupts = <32>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; starfive,signal-group = <6>; gmac_pins_default: gmac-0 { gtxclk-pins { pins = ; bias-pull-up; drive-strength = <35>; input-enable; input-schmitt-enable; slew-rate = <0>; }; miitxclk-pins { pins = ; bias-pull-up; drive-strength = <14>; input-enable; input-schmitt-disable; slew-rate = <0>; }; tx-pins { pins = , , , , , , , , ; bias-disable; drive-strength = <35>; input-disable; input-schmitt-disable; slew-rate = <0>; }; rxclk-pins { pins = ; bias-pull-up; drive-strength = <14>; input-enable; input-schmitt-disable; slew-rate = <6>; }; rxer-pins { pins = ; bias-pull-up; drive-strength = <14>; input-enable; input-schmitt-disable; slew-rate = <0>; }; rx-pins { pins = , , , , , , , , , , , , ; bias-pull-up; drive-strength = <14>; input-enable; input-schmitt-enable; slew-rate = <0>; }; }; i2c0_pins_default: i2c0-0 { i2c-pins { pinmux = , ; bias-disable; /* external pull-up */ input-enable; input-schmitt-enable; }; }; uart3_pins_default: uart3-0 { rx-pins { pinmux = ; bias-pull-up; input-enable; input-schmitt-enable; }; tx-pins { pinmux = ; bias-disable; input-disable; input-schmitt-disable; }; }; }; gmac { pinctrl-0 = <&gmac_pins_default>; pinctrl-names = "default"; }; i2c { pinctrl-0 = <&i2c0_pins_default>; pinctrl-names = "default"; }; uart3 { pinctrl-0 = <&uart3_pins_default>; pinctrl-names = "default"; }; }; ...