# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx SuperSpeed DWC3 USB SoC controller maintainers: - Mubin Sayyed - Radhey Shyam Pandey properties: compatible: items: - enum: - xlnx,zynqmp-dwc3 - xlnx,versal-dwc3 reg: maxItems: 1 "#address-cells": enum: [ 1, 2 ] "#size-cells": enum: [ 1, 2 ] ranges: true power-domains: description: specifies a phandle to PM domain provider node maxItems: 1 clocks: description: A list of phandle and clock-specifier pairs for the clocks listed in clock-names. items: - description: Master/Core clock, has to be >= 125 MHz for SS operation and >= 60MHz for HS operation. - description: Clock source to core during PHY power down. clock-names: items: - const: bus_clk - const: ref_clk resets: description: A list of phandles for resets listed in reset-names. items: - description: USB core reset - description: USB hibernation reset - description: USB APB reset reset-names: items: - const: usb_crst - const: usb_hibrst - const: usb_apbrst phys: minItems: 1 maxItems: 2 phy-names: minItems: 1 maxItems: 2 items: enum: - usb2-phy - usb3-phy reset-gpios: description: GPIO used for the reset ulpi-phy maxItems: 1 # Required child node: patternProperties: "^usb@[0-9a-f]+$": $ref: snps,dwc3.yaml# required: - compatible - reg - "#address-cells" - "#size-cells" - ranges - power-domains - clocks - clock-names - resets - reset-names additionalProperties: false examples: - | #include #include #include #include #include #include axi { #address-cells = <2>; #size-cells = <2>; usb@0 { #address-cells = <0x2>; #size-cells = <0x2>; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; phy-names = "usb3-phy"; ranges; usb@fe200000 { compatible = "snps,dwc3"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-names = "host", "otg"; interrupts = <0 65 4>, <0 69 4>; dr_mode = "host"; dma-coherent; }; }; };