# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm SuperSpeed DWC3 USB SoC controller maintainers: - Wesley Cheng properties: compatible: items: - enum: - qcom,ipq4019-dwc3 - qcom,ipq5018-dwc3 - qcom,ipq5332-dwc3 - qcom,ipq6018-dwc3 - qcom,ipq8064-dwc3 - qcom,ipq8074-dwc3 - qcom,ipq9574-dwc3 - qcom,msm8953-dwc3 - qcom,msm8994-dwc3 - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 - qcom,qcm2290-dwc3 - qcom,qcs404-dwc3 - qcom,sa8775p-dwc3 - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 - qcom,sc8280xp-dwc3 - qcom,sdm660-dwc3 - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 - qcom,sdx65-dwc3 - qcom,sdx75-dwc3 - qcom,sm4250-dwc3 - qcom,sm6115-dwc3 - qcom,sm6125-dwc3 - qcom,sm6350-dwc3 - qcom,sm6375-dwc3 - qcom,sm8150-dwc3 - qcom,sm8250-dwc3 - qcom,sm8350-dwc3 - qcom,sm8450-dwc3 - qcom,sm8550-dwc3 - qcom,sm8650-dwc3 - qcom,x1e80100-dwc3 - const: qcom,dwc3 reg: description: Offset and length of register set for QSCRATCH wrapper maxItems: 1 "#address-cells": enum: [ 1, 2 ] "#size-cells": enum: [ 1, 2 ] ranges: true power-domains: description: specifies a phandle to PM domain provider node maxItems: 1 required-opps: maxItems: 1 clocks: description: | Several clocks are used, depending on the variant. Typical ones are:: - cfg_noc:: System Config NOC clock. - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= 60MHz for HS operation. - iface:: System bus AXI clock. - sleep:: Sleep clock, used for wakeup when USB3 core goes into low power mode (U3). - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host mode. Its frequency should be 19.2MHz. minItems: 1 maxItems: 9 clock-names: minItems: 1 maxItems: 9 resets: maxItems: 1 interconnects: maxItems: 2 interconnect-names: items: - const: usb-ddr - const: apps-usb interrupts: description: | Different types of interrupts are used based on HS PHY used on target: - pwr_event: Used for wakeup based on other power events. - hs_phY_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is hs_phy_irq which is not triggered by default and its functionality is mutually exclusive to that of {dp/dm}_hs_phy_irq and qusb2_phy_irq. - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and expose only a single IRQ whose behavior can be modified by the QUSB2PHY_INTR_CTRL register. The required DPSE/ DMSE configuration is done in QUSB2PHY_INTR_CTRL register of PHY address space. - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/ DM pads of the SoC. These are used for wakeup only on SoCs with non-QUSB2 targets with exception of SDM670/SDM845/SM6350. - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation. minItems: 2 maxItems: 5 interrupt-names: minItems: 2 maxItems: 5 qcom,select-utmi-as-pipe-clk: description: If present, disable USB3 pipe_clk requirement. Used when dwc3 operates without SSPHY and only HS/FS/LS modes are supported. type: boolean wakeup-source: true # Required child node: patternProperties: "^usb@[0-9a-f]+$": $ref: snps,dwc3.yaml# unevaluatedProperties: false properties: wakeup-source: false required: - compatible - reg - "#address-cells" - "#size-cells" - ranges - clocks - clock-names - interrupts - interrupt-names allOf: - if: properties: compatible: contains: enum: - qcom,ipq4019-dwc3 then: properties: clocks: maxItems: 3 clock-names: items: - const: core - const: sleep - const: mock_utmi - if: properties: compatible: contains: enum: - qcom,ipq8064-dwc3 then: properties: clocks: items: - description: Master/Core clock, has to be >= 125 MHz for SS operation and >= 60MHz for HS operation. clock-names: items: - const: core - if: properties: compatible: contains: enum: - qcom,ipq9574-dwc3 - qcom,msm8953-dwc3 - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 - qcom,sa8775p-dwc3 - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 - qcom,sdx65-dwc3 - qcom,sdx75-dwc3 - qcom,sm6350-dwc3 then: properties: clocks: maxItems: 5 clock-names: items: - const: cfg_noc - const: core - const: iface - const: sleep - const: mock_utmi - if: properties: compatible: contains: enum: - qcom,ipq6018-dwc3 then: properties: clocks: minItems: 3 maxItems: 4 clock-names: oneOf: - items: - const: core - const: sleep - const: mock_utmi - items: - const: cfg_noc - const: core - const: sleep - const: mock_utmi - if: properties: compatible: contains: enum: - qcom,ipq8074-dwc3 then: properties: clocks: maxItems: 4 clock-names: items: - const: cfg_noc - const: core - const: sleep - const: mock_utmi - if: properties: compatible: contains: enum: - qcom,ipq5018-dwc3 - qcom,ipq5332-dwc3 - qcom,msm8994-dwc3 - qcom,qcs404-dwc3 then: properties: clocks: maxItems: 4 clock-names: items: - const: core - const: iface - const: sleep - const: mock_utmi - if: properties: compatible: contains: enum: - qcom,sc8280xp-dwc3 - qcom,x1e80100-dwc3 then: properties: clocks: maxItems: 9 clock-names: items: - const: cfg_noc - const: core - const: iface - const: sleep - const: mock_utmi - const: noc_aggr - const: noc_aggr_north - const: noc_aggr_south - const: noc_sys - if: properties: compatible: contains: enum: - qcom,sdm660-dwc3 then: properties: clocks: minItems: 4 maxItems: 5 clock-names: oneOf: - items: - const: cfg_noc - const: core - const: iface - const: sleep - const: mock_utmi - items: - const: cfg_noc - const: core - const: sleep - const: mock_utmi - if: properties: compatible: contains: enum: - qcom,qcm2290-dwc3 - qcom,sm6115-dwc3 - qcom,sm6125-dwc3 - qcom,sm8150-dwc3 - qcom,sm8250-dwc3 - qcom,sm8450-dwc3 - qcom,sm8550-dwc3 - qcom,sm8650-dwc3 then: properties: clocks: minItems: 6 clock-names: items: - const: cfg_noc - const: core - const: iface - const: sleep - const: mock_utmi - const: xo - if: properties: compatible: contains: enum: - qcom,sm8350-dwc3 then: properties: clocks: minItems: 5 maxItems: 6 clock-names: minItems: 5 items: - const: cfg_noc - const: core - const: iface - const: sleep - const: mock_utmi - const: xo - if: properties: compatible: contains: enum: - qcom,ipq5018-dwc3 - qcom,ipq6018-dwc3 - qcom,ipq8074-dwc3 - qcom,msm8953-dwc3 - qcom,msm8998-dwc3 then: properties: interrupts: minItems: 2 maxItems: 3 interrupt-names: items: - const: pwr_event - const: qusb2_phy - const: ss_phy_irq - if: properties: compatible: contains: enum: - qcom,msm8996-dwc3 - qcom,qcs404-dwc3 - qcom,sdm660-dwc3 - qcom,sm6115-dwc3 - qcom,sm6125-dwc3 then: properties: interrupts: minItems: 3 maxItems: 4 interrupt-names: items: - const: pwr_event - const: qusb2_phy - const: hs_phy_irq - const: ss_phy_irq - if: properties: compatible: contains: enum: - qcom,ipq5332-dwc3 - qcom,x1e80100-dwc3 then: properties: interrupts: maxItems: 4 interrupt-names: items: - const: pwr_event - const: dp_hs_phy_irq - const: dm_hs_phy_irq - const: ss_phy_irq - if: properties: compatible: contains: enum: - qcom,ipq4019-dwc3 - qcom,ipq8064-dwc3 - qcom,msm8994-dwc3 - qcom,sa8775p-dwc3 - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 - qcom,sc8280xp-dwc3 - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 - qcom,sdx65-dwc3 - qcom,sdx75-dwc3 - qcom,sm4250-dwc3 - qcom,sm6350-dwc3 - qcom,sm8150-dwc3 - qcom,sm8250-dwc3 - qcom,sm8350-dwc3 - qcom,sm8450-dwc3 - qcom,sm8550-dwc3 - qcom,sm8650-dwc3 then: properties: interrupts: minItems: 4 maxItems: 5 interrupt-names: items: - const: pwr_event - const: hs_phy_irq - const: dp_hs_phy_irq - const: dm_hs_phy_irq - const: ss_phy_irq additionalProperties: false examples: - | #include #include #include soc { #address-cells = <2>; #size-cells = <2>; usb@a6f8800 { compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_SLEEP_CLK>, <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; interrupts = , , , , ; interrupt-names = "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; resets = <&gcc GCC_USB30_PRIM_BCR>; usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; interrupts = ; iommus = <&apps_smmu 0x740 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_ssphy>; phy-names = "usb2-phy", "usb3-phy"; }; }; };