/* * Broadcom BCM470X / BCM5301X ARM platform code. * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs * * Copyright 2013-2014 Hauke Mehrtens * * Licensed under the GNU/GPL. See COPYING for details. */ #include #include #include "skeleton.dtsi" / { interrupt-parent = <&gic>; chipcommonA { compatible = "simple-bus"; ranges = <0x00000000 0x18000000 0x00001000>; #address-cells = <1>; #size-cells = <1>; uart0: serial@0300 { compatible = "ns16550"; reg = <0x0300 0x100>; interrupts = ; clock-frequency = <100000000>; status = "disabled"; }; uart1: serial@0400 { compatible = "ns16550"; reg = <0x0400 0x100>; interrupts = ; clock-frequency = <100000000>; status = "disabled"; }; }; mpcore { compatible = "simple-bus"; ranges = <0x00000000 0x19020000 0x00003000>; #address-cells = <1>; #size-cells = <1>; scu@0000 { compatible = "arm,cortex-a9-scu"; reg = <0x0000 0x100>; }; timer@0200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x0200 0x100>; interrupts = ; clocks = <&clk_periph>; }; local-timer@0600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x0600 0x100>; interrupts = ; clocks = <&clk_periph>; }; gic: interrupt-controller@1000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x1000 0x1000>, <0x0100 0x100>; }; L2: cache-controller@2000 { compatible = "arm,pl310-cache"; reg = <0x2000 0x1000>; cache-unified; cache-level = <2>; }; }; clocks { #address-cells = <1>; #size-cells = <0>; /* As long as we do not have a real clock driver us this * fixed clock */ clk_periph: periph { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <400000000>; }; }; };