/* * Copyright 2012 Denis 'GNUtoo' Carikli * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: * * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ / { #address-cells = <1>; #size-cells = <1>; /* * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; memory { device_type = "memory"; }; aliases { serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,arm1136jf-s"; device_type = "cpu"; reg = <0>; }; }; avic: interrupt-controller@68000000 { compatible = "fsl,imx31-avic", "fsl,avic"; interrupt-controller; #interrupt-cells = <1>; reg = <0x68000000 0x100000>; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&avic>; ranges; aips@43f00000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x43f00000 0x100000>; ranges; uart1: serial@43f90000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43f90000 0x4000>; interrupts = <45>; clocks = <&clks 10>, <&clks 30>; clock-names = "ipg", "per"; status = "disabled"; }; uart2: serial@43f94000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43f94000 0x4000>; interrupts = <32>; clocks = <&clks 10>, <&clks 31>; clock-names = "ipg", "per"; status = "disabled"; }; kpp: kpp@43fa8000 { compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; reg = <0x43fa8000 0x4000>; interrupts = <24>; clocks = <&clks 46>; status = "disabled"; }; uart4: serial@43fb0000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43fb0000 0x4000>; clocks = <&clks 10>, <&clks 49>; clock-names = "ipg", "per"; interrupts = <46>; status = "disabled"; }; uart5: serial@43fb4000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43fb4000 0x4000>; interrupts = <47>; clocks = <&clks 10>, <&clks 50>; clock-names = "ipg", "per"; status = "disabled"; }; }; spba@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x50000000 0x100000>; ranges; uart3: serial@5000c000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; interrupts = <18>; clocks = <&clks 10>, <&clks 48>; clock-names = "ipg", "per"; status = "disabled"; }; iim: iim@5001c000 { compatible = "fsl,imx31-iim", "fsl,imx27-iim"; reg = <0x5001c000 0x1000>; interrupts = <19>; clocks = <&clks 25>; }; }; aips@53f00000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x53f00000 0x100000>; ranges; clks: ccm@53f80000{ compatible = "fsl,imx31-ccm"; reg = <0x53f80000 0x4000>; interrupts = <31>, <53>; #clock-cells = <1>; }; gpt: timer@53f90000 { compatible = "fsl,imx31-gpt"; reg = <0x53f90000 0x4000>; interrupts = <29>; clocks = <&clks 10>, <&clks 22>; clock-names = "ipg", "per"; }; }; }; };