// SPDX-License-Identifier: GPL-2.0
/*
 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
 *
 * Copyright (C) 2018 Renesas Electronics Europe Limited
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a06g032-sysctrl.h>

/ {
	compatible = "renesas,r9a06g032";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
			enable-method = "renesas,r9a06g032-smp";
			cpu-release-addr = <0 0x4000c204>;
		};
	};

	ext_jtag_clk: extjtagclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	ext_mclk: extmclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <40000000>;
	};

	ext_rgmii_ref: extrgmiiref {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	ext_rtc_clk: extrtcclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;
		ranges;

		sysctrl: system-controller@4000c000 {
			compatible = "renesas,r9a06g032-sysctrl";
			reg = <0x4000c000 0x1000>;
			status = "okay";
			#clock-cells = <1>;

			clocks = <&ext_mclk>, <&ext_rtc_clk>,
					<&ext_jtag_clk>, <&ext_rgmii_ref>;
			clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
		};

		uart0: serial@40060000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40060000 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart1: serial@40061000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40061000 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart2: serial@40062000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40062000 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart3: serial@50000000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50000000 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart4: serial@50001000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50001000 0x400>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart5: serial@50002000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50002000 0x400>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart6: serial@50003000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50003000 0x400>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart7: serial@50004000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50004000 0x400>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		pinctrl: pin-controller@40067000 {
			compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
			reg = <0x40067000 0x1000>, <0x51000000 0x480>;
			clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
			clock-names = "bus";
			status = "okay";
		};

		gic: interrupt-controller@44101000 {
			compatible = "arm,cortex-a7-gic", "arm,gic-400";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x44101000 0x1000>, /* Distributer */
			      <0x44102000 0x2000>, /* CPU interface */
			      <0x44104000 0x2000>, /* Virt interface control */
			      <0x44106000 0x2000>; /* Virt CPU interface */
			interrupts =
				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
		};
	};

	timer {
		compatible = "arm,cortex-a7-timer",
			     "arm,armv7-timer";
		interrupt-parent = <&gic>;
		arm,cpu-registers-not-fw-configured;
		always-on;
		interrupts =
			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};
};