/*
 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
 *
 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/axg-clkc.h>

/ {
	compatible = "amlogic,meson-axg";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* 16 MiB reserved for Hardware ROM Firmware */
		hwrom_reserved: hwrom@0 {
			reg = <0x0 0x0 0x0 0x1000000>;
			no-map;
		};

		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
		secmon_reserved: secmon@5000000 {
			reg = <0x0 0x05000000 0x0 0x300000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x2>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0 0x3>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		l2: l2-cache0 {
			compatible = "cache";
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
	};

	xtal: xtal-clk {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xtal";
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		cbus: bus@ffd00000 {
			compatible = "simple-bus";
			reg = <0x0 0xffd00000 0x0 0x25000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;

			pwm_ab: pwm@1b000 {
				compatible = "amlogic,meson-axg-ee-pwm";
				reg = <0x0 0x1b000 0x0 0x20>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm_cd: pwm@1a000 {
				compatible = "amlogic,meson-axg-ee-pwm";
				reg = <0x0 0x1a000 0x0 0x20>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			reset: reset-controller@1004 {
				compatible = "amlogic,meson-axg-reset";
				reg = <0x0 0x01004 0x0 0x9c>;
				#reset-cells = <1>;
			};

			spicc0: spi@13000 {
				compatible = "amlogic,meson-axg-spicc";
				reg = <0x0 0x13000 0x0 0x3c>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clkc CLKID_SPICC0>;
				clock-names = "core";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spicc1: spi@15000 {
				compatible = "amlogic,meson-axg-spicc";
				reg = <0x0 0x15000 0x0 0x3c>;
				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clkc CLKID_SPICC1>;
				clock-names = "core";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			uart_A: serial@24000 {
				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
				reg = <0x0 0x24000 0x0 0x18>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			uart_B: serial@23000 {
				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
				reg = <0x0 0x23000 0x0 0x18>;
				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};
		};

		ethmac: ethernet@ff3f0000 {
			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
			reg = <0x0 0xff3f0000 0x0 0x10000
				0x0 0xff634540 0x0 0x8>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "macirq";
			clocks = <&clkc CLKID_ETH>,
				 <&clkc CLKID_FCLK_DIV2>,
				 <&clkc CLKID_MPLL2>;
			clock-names = "stmmaceth", "clkin0", "clkin1";
			status = "disabled";
		};

		gic: interrupt-controller@ffc01000 {
			compatible = "arm,gic-400";
			reg = <0x0 0xffc01000 0 0x1000>,
			      <0x0 0xffc02000 0 0x2000>,
			      <0x0 0xffc04000 0 0x2000>,
			      <0x0 0xffc06000 0 0x2000>;
			interrupt-controller;
			interrupts = <GIC_PPI 9
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
			#interrupt-cells = <3>;
			#address-cells = <0>;
		};

		hiubus: bus@ff63c000 {
			compatible = "simple-bus";
			reg = <0x0 0xff63c000 0x0 0x1c00>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;

			clkc: clock-controller@0 {
				compatible = "amlogic,axg-clkc";
				#clock-cells = <1>;
				reg = <0x0 0x0 0x0 0x320>;
			};
		};

		mailbox: mailbox@ff63dc00 {
			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
			reg = <0 0xff63dc00 0 0x400>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
			#mbox-cells = <1>;
		};

		periphs: periphs@ff634000 {
			compatible = "simple-bus";
			reg = <0x0 0xff634000 0x0 0x2000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;

			pinctrl_periphs: pinctrl@480 {
				compatible = "amlogic,meson-axg-periphs-pinctrl";
				#address-cells = <2>;
				#size-cells = <2>;
				ranges;

				gpio: bank@480 {
					reg = <0x0 0x00480 0x0 0x40>,
						<0x0 0x004e8 0x0 0x14>,
						<0x0 0x00520 0x0 0x14>,
						<0x0 0x00430 0x0 0x3c>;
					reg-names = "mux", "pull", "pull-enable", "gpio";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&pinctrl_periphs 0 0 86>;
				};

				eth_rgmii_x_pins: eth-x-rgmii {
					mux {
						groups = "eth_mdio_x",
						       "eth_mdc_x",
						       "eth_rgmii_rx_clk_x",
						       "eth_rx_dv_x",
						       "eth_rxd0_x",
						       "eth_rxd1_x",
						       "eth_rxd2_rgmii",
						       "eth_rxd3_rgmii",
						       "eth_rgmii_tx_clk",
						       "eth_txen_x",
						       "eth_txd0_x",
						       "eth_txd1_x",
						       "eth_txd2_rgmii",
						       "eth_txd3_rgmii";
						function = "eth";
					};
				};

				eth_rgmii_y_pins: eth-y-rgmii {
					mux {
						groups = "eth_mdio_y",
						       "eth_mdc_y",
						       "eth_rgmii_rx_clk_y",
						       "eth_rx_dv_y",
						       "eth_rxd0_y",
						       "eth_rxd1_y",
						       "eth_rxd2_rgmii",
						       "eth_rxd3_rgmii",
						       "eth_rgmii_tx_clk",
						       "eth_txen_y",
						       "eth_txd0_y",
						       "eth_txd1_y",
						       "eth_txd2_rgmii",
						       "eth_txd3_rgmii";
						function = "eth";
					};
				};

				pwm_a_a_pins: pwm_a_a {
					mux {
						groups = "pwm_a_a";
						function = "pwm_a";
					};
				};

				pwm_a_x18_pins: pwm_a_x18 {
					mux {
						groups = "pwm_a_x18";
						function = "pwm_a";
					};
				};

				pwm_a_x20_pins: pwm_a_x20 {
					mux {
						groups = "pwm_a_x20";
						function = "pwm_a";
					};
				};

				pwm_a_z_pins: pwm_a_z {
					mux {
						groups = "pwm_a_z";
						function = "pwm_a";
					};
				};

				pwm_b_a_pins: pwm_b_a {
					mux {
						groups = "pwm_b_a";
						function = "pwm_b";
					};
				};

				pwm_b_x_pins: pwm_b_x {
					mux {
						groups = "pwm_b_x";
						function = "pwm_b";
					};
				};

				pwm_b_z_pins: pwm_b_z {
					mux {
						groups = "pwm_b_z";
						function = "pwm_b";
					};
				};

				pwm_c_a_pins: pwm_c_a {
					mux {
						groups = "pwm_c_a";
						function = "pwm_c";
					};
				};

				pwm_c_x10_pins: pwm_c_x10 {
					mux {
						groups = "pwm_c_x10";
						function = "pwm_c";
					};
				};

				pwm_c_x17_pins: pwm_c_x17 {
					mux {
						groups = "pwm_c_x17";
						function = "pwm_c";
					};
				};

				pwm_d_x11_pins: pwm_d_x11 {
					mux {
						groups = "pwm_d_x11";
						function = "pwm_d";
					};
				};

				pwm_d_x16_pins: pwm_d_x16 {
					mux {
						groups = "pwm_d_x16";
						function = "pwm_d";
					};
				};

				spi0_pins: spi0 {
					mux {
						groups = "spi0_miso",
							"spi0_mosi",
							"spi0_clk";
						function = "spi0";
					};
				};

				spi0_ss0_pins: spi0_ss0 {
					mux {
						groups = "spi0_ss0";
						function = "spi0";
					};
				};

				spi0_ss1_pins: spi0_ss1 {
					mux {
						groups = "spi0_ss1";
						function = "spi0";
					};
				};

				spi0_ss2_pins: spi0_ss2 {
					mux {
						groups = "spi0_ss2";
						function = "spi0";
					};
				};


				spi1_a_pins: spi1_a {
					mux {
						groups = "spi1_miso_a",
							"spi1_mosi_a",
							"spi1_clk_a";
						function = "spi1";
					};
				};

				spi1_ss0_a_pins: spi1_ss0_a {
					mux {
						groups = "spi1_ss0_a";
						function = "spi1";
					};
				};

				spi1_ss1_pins: spi1_ss1 {
					mux {
						groups = "spi1_ss1";
						function = "spi1";
					};
				};

				spi1_x_pins: spi1_x {
					mux {
						groups = "spi1_miso_x",
							"spi1_mosi_x",
							"spi1_clk_x";
						function = "spi1";
					};
				};

				spi1_ss0_x_pins: spi1_ss0_x {
					mux {
						groups = "spi1_ss0_x";
						function = "spi1";
					};
				};
			};
		};

		sram: sram@fffc0000 {
			compatible = "amlogic,meson-axg-sram", "mmio-sram";
			reg = <0x0 0xfffc0000 0x0 0x20000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x0 0xfffc0000 0x20000>;

			cpu_scp_lpri: scp-shmem@0 {
				compatible = "amlogic,meson-axg-scp-shmem";
				reg = <0x13000 0x400>;
			};

			cpu_scp_hpri: scp-shmem@200 {
				compatible = "amlogic,meson-axg-scp-shmem";
				reg = <0x13400 0x400>;
			};
		};

		aobus: bus@ff800000 {
			compatible = "simple-bus";
			reg = <0x0 0xff800000 0x0 0x100000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;

			pinctrl_aobus: pinctrl@14 {
				compatible = "amlogic,meson-axg-aobus-pinctrl";
				#address-cells = <2>;
				#size-cells = <2>;
				ranges;

				gpio_ao: bank@14 {
					reg = <0x0 0x00014 0x0 0x8>,
						<0x0 0x0002c 0x0 0x4>,
						<0x0 0x00024 0x0 0x8>;
					reg-names = "mux", "pull", "gpio";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&pinctrl_aobus 0 0 15>;
				};

				remote_input_ao_pins: remote_input_ao {
					mux {
						groups = "remote_input_ao";
						function = "remote_input_ao";
					};
				};
			};

			pwm_AO_ab: pwm@7000 {
				compatible = "amlogic,meson-axg-ao-pwm";
				reg = <0x0 0x07000 0x0 0x20>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm_AO_cd: pwm@2000 {
				compatible = "amlogic,axg-ao-pwm";
				reg = <0x0 0x02000  0x0 0x20>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			uart_AO: serial@3000 {
				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
				reg = <0x0 0x3000 0x0 0x18>;
				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
				clock-names = "xtal", "pclk", "baud";
				status = "disabled";
			};

			uart_AO_B: serial@4000 {
				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
				reg = <0x0 0x4000 0x0 0x18>;
				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
				clock-names = "xtal", "pclk", "baud";
				status = "disabled";
			};

			ir: ir@8000 {
				compatible = "amlogic,meson-gxbb-ir";
				reg = <0x0 0x8000 0x0 0x20>;
				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};
		};
	};
};