// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for NXP Layerscape-1028A family SoC. * * Copyright 2018 NXP * * Harninder Rai * */ #include #include / { compatible = "fsl,ls1028a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0>; enable-method = "psci"; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x1>; enable-method = "psci"; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; }; l2: l2-cache { compatible = "cache"; }; }; idle-states { /* * PSCI node is not added default, U-boot will add missing * parts if it determines to use PSCI. */ entry-method = "arm,psci"; CPU_PH20: cpu-ph20 { compatible = "arm,idle-state"; idle-state-name = "PH20"; arm,psci-suspend-param = <0x00010000>; entry-latency-us = <1000>; exit-latency-us = <1000>; min-residency-us = <3000>; }; }; sysclk: clock-sysclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "sysclk"; }; reboot { compatible ="syscon-reboot"; regmap = <&dcfg>; offset = <0xb0>; mask = <0x02>; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , ; }; gic: interrupt-controller@6000000 { compatible= "arm,gic-v3"; #address-cells = <2>; #size-cells = <2>; ranges; reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ #interrupt-cells= <3>; interrupt-controller; interrupts = ; its: gic-its@6020000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ }; }; soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; ddr: memory-controller@1080000 { compatible = "fsl,qoriq-memory-controller"; reg = <0x0 0x1080000 0x0 0x1000>; interrupts = ; big-endian; }; dcfg: syscon@1e00000 { compatible = "fsl,ls1028a-dcfg", "syscon"; reg = <0x0 0x1e00000 0x0 0x10000>; big-endian; }; scfg: syscon@1fc0000 { compatible = "fsl,ls1028a-scfg", "syscon"; reg = <0x0 0x1fc0000 0x0 0x10000>; big-endian; }; clockgen: clock-controller@1300000 { compatible = "fsl,ls1028a-clockgen"; reg = <0x0 0x1300000 0x0 0xa0000>; #clock-cells = <2>; clocks = <&sysclk>; }; i2c0: i2c@2000000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; i2c1: i2c@2010000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; i2c2: i2c@2020000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; i2c3: i2c@2030000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; i2c4: i2c@2040000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2040000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; i2c5: i2c@2050000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2050000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; i2c6: i2c@2060000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2060000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; i2c7: i2c@2070000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2070000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0600 0x0 0x100>; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; gpio1: gpio@2300000 { compatible = "fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio2: gpio@2310000 { compatible = "fsl,qoriq-gpio"; reg = <0x0 0x2310000 0x0 0x10000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio3: gpio@2320000 { compatible = "fsl,qoriq-gpio"; reg = <0x0 0x2320000 0x0 0x10000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; wdog0: watchdog@23c0000 { compatible = "fsl,ls1028a-wdt", "fsl,imx21-wdt"; reg = <0x0 0x23c0000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; big-endian; status = "disabled"; }; sata: sata@3200000 { compatible = "fsl,ls1028a-ahci"; reg = <0x0 0x3200000 0x0 0x10000>, <0x0 0x20140520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = ; clocks = <&clockgen 4 1>; status = "disabled"; }; smmu: iommu@5000000 { compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; #global-interrupts = <8>; #iommu-cells = <1>; stream-match-mask = <0x7c00>; /* global secure fault */ interrupts = , /* combined secure interrupt */ , /* global non-secure fault */ , /* combined non-secure interrupt */ , /* performance counter interrupts 0-7 */ , , , , /* per context interrupt, 64 interrupts */ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ; }; }; };