/*
 * Copyright (c) 2017 MediaTek Inc.
 * Author: YT Shen <yt.shen@mediatek.com>
 *
 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
 */

#include <dt-bindings/clock/mt2712-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/mt2712-power.h>
#include "mt2712-pinfunc.h"

/ {
	compatible = "mediatek,mt2712";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	cluster0_opp: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;
		opp00 {
			opp-hz = /bits/ 64 <598000000>;
			opp-microvolt = <1000000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <702000000>;
			opp-microvolt = <1000000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <793000000>;
			opp-microvolt = <1000000>;
		};
	};

	cluster1_opp: opp_table1 {
		compatible = "operating-points-v2";
		opp-shared;
		opp00 {
			opp-hz = /bits/ 64 <598000000>;
			opp-microvolt = <1000000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <702000000>;
			opp-microvolt = <1000000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <793000000>;
			opp-microvolt = <1000000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <897000000>;
			opp-microvolt = <1000000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1001000000>;
			opp-microvolt = <1000000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu2>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x000>;
			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
				<&topckgen CLK_TOP_F_MP0_PLL1>;
			clock-names = "cpu", "intermediate";
			proc-supply = <&cpus_fixed_vproc0>;
			operating-points-v2 = <&cluster0_opp>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x001>;
			enable-method = "psci";
			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
				<&topckgen CLK_TOP_F_MP0_PLL1>;
			clock-names = "cpu", "intermediate";
			proc-supply = <&cpus_fixed_vproc0>;
			operating-points-v2 = <&cluster0_opp>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x200>;
			enable-method = "psci";
			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
				<&topckgen CLK_TOP_F_BIG_PLL1>;
			clock-names = "cpu", "intermediate";
			proc-supply = <&cpus_fixed_vproc1>;
			operating-points-v2 = <&cluster1_opp>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				entry-latency-us = <100>;
				exit-latency-us = <80>;
				min-residency-us = <2000>;
				arm,psci-suspend-param = <0x0010000>;
			};

			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				entry-latency-us = <350>;
				exit-latency-us = <80>;
				min-residency-us = <3000>;
				arm,psci-suspend-param = <0x1010000>;
			};
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	baud_clk: dummy26m {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	sys_clk: dummyclk {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	clk26m: oscillator@0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	clk32k: oscillator@1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "clk32k";
	};

	clkfpc: oscillator@2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
		clock-output-names = "clkfpc";
	};

	clkaud_ext_i_0: oscillator@3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <6500000>;
		clock-output-names = "clkaud_ext_i_0";
	};

	clkaud_ext_i_1: oscillator@4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <196608000>;
		clock-output-names = "clkaud_ext_i_1";
	};

	clkaud_ext_i_2: oscillator@5 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <180633600>;
		clock-output-names = "clkaud_ext_i_2";
	};

	clki2si0_mck_i: oscillator@6 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <30000000>;
		clock-output-names = "clki2si0_mck_i";
	};

	clki2si1_mck_i: oscillator@7 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <30000000>;
		clock-output-names = "clki2si1_mck_i";
	};

	clki2si2_mck_i: oscillator@8 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <30000000>;
		clock-output-names = "clki2si2_mck_i";
	};

	clktdmin_mclk_i: oscillator@9 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <30000000>;
		clock-output-names = "clktdmin_mclk_i";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13
			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
	};

	topckgen: syscon@10000000 {
		compatible = "mediatek,mt2712-topckgen", "syscon";
		reg = <0 0x10000000 0 0x1000>;
		#clock-cells = <1>;
	};

	infracfg: syscon@10001000 {
		compatible = "mediatek,mt2712-infracfg", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		#clock-cells = <1>;
	};

	pericfg: syscon@10003000 {
		compatible = "mediatek,mt2712-pericfg", "syscon";
		reg = <0 0x10003000 0 0x1000>;
		#clock-cells = <1>;
	};

	syscfg_pctl_a: syscfg_pctl_a@10005000 {
		compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
		reg = <0 0x10005000 0 0x1000>;
	};

	pio: pinctrl@10005000 {
		compatible = "mediatek,mt2712-pinctrl";
		reg = <0 0x1000b000 0 0x1000>;
		mediatek,pctl-regmap = <&syscfg_pctl_a>;
		pins-are-numbered;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	};

	scpsys: scpsys@10006000 {
		compatible = "mediatek,mt2712-scpsys", "syscon";
		#power-domain-cells = <1>;
		reg = <0 0x10006000 0 0x1000>;
		clocks = <&topckgen CLK_TOP_MM_SEL>,
			 <&topckgen CLK_TOP_MFG_SEL>,
			 <&topckgen CLK_TOP_VENC_SEL>,
			 <&topckgen CLK_TOP_JPGDEC_SEL>,
			 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
			 <&topckgen CLK_TOP_VDEC_SEL>;
		clock-names = "mm", "mfg", "venc",
			"jpgdec", "audio", "vdec";
		infracfg = <&infracfg>;
	};

	uart5: serial@1000f000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x1000f000 0 0x400>;
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	spis1: spi@10013000 {
		compatible = "mediatek,mt2712-spi-slave";
		reg = <0 0x10013000 0 0x100>;
		interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg CLK_INFRA_AO_SPI1>;
		clock-names = "spi";
		assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
		status = "disabled";
	};

	apmixedsys: syscon@10209000 {
		compatible = "mediatek,mt2712-apmixedsys", "syscon";
		reg = <0 0x10209000 0 0x1000>;
		#clock-cells = <1>;
	};

	mcucfg: syscon@10220000 {
		compatible = "mediatek,mt2712-mcucfg", "syscon";
		reg = <0 0x10220000 0 0x1000>;
		#clock-cells = <1>;
	};

	sysirq: interrupt-controller@10220a80 {
		compatible = "mediatek,mt2712-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10220a80 0 0x40>;
	};

	gic: interrupt-controller@10510000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		interrupt-controller;
		reg = <0 0x10510000 0 0x10000>,
		      <0 0x10520000 0 0x20000>,
		      <0 0x10540000 0 0x20000>,
		      <0 0x10560000 0 0x20000>;
		interrupts = <GIC_PPI 9
			 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	auxadc: adc@11001000 {
		compatible = "mediatek,mt2712-auxadc";
		reg = <0 0x11001000 0 0x1000>;
		clocks = <&pericfg CLK_PERI_AUXADC>;
		clock-names = "main";
		#io-channel-cells = <1>;
		status = "disabled";
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11004000 0 0x400>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11005000 0 0x400>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart4: serial@11019000 {
		compatible = "mediatek,mt2712-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11019000 0 0x400>;
		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&baud_clk>, <&sys_clk>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	mfgcfg: syscon@13000000 {
		compatible = "mediatek,mt2712-mfgcfg", "syscon";
		reg = <0 0x13000000 0 0x1000>;
		#clock-cells = <1>;
	};

	mmsys: syscon@14000000 {
		compatible = "mediatek,mt2712-mmsys", "syscon";
		reg = <0 0x14000000 0 0x1000>;
		#clock-cells = <1>;
	};

	imgsys: syscon@15000000 {
		compatible = "mediatek,mt2712-imgsys", "syscon";
		reg = <0 0x15000000 0 0x1000>;
		#clock-cells = <1>;
	};

	bdpsys: syscon@15010000 {
		compatible = "mediatek,mt2712-bdpsys", "syscon";
		reg = <0 0x15010000 0 0x1000>;
		#clock-cells = <1>;
	};

	vdecsys: syscon@16000000 {
		compatible = "mediatek,mt2712-vdecsys", "syscon";
		reg = <0 0x16000000 0 0x1000>;
		#clock-cells = <1>;
	};

	vencsys: syscon@18000000 {
		compatible = "mediatek,mt2712-vencsys", "syscon";
		reg = <0 0x18000000 0 0x1000>;
		#clock-cells = <1>;
	};

	jpgdecsys: syscon@19000000 {
		compatible = "mediatek,mt2712-jpgdecsys", "syscon";
		reg = <0 0x19000000 0 0x1000>;
		#clock-cells = <1>;
	};
};