// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2020 MediaTek Inc.
 * Copyright (c) 2020 BayLibre, SAS.
 * Author: Fabien Parent <fparent@baylibre.com>
 */

#include <dt-bindings/clock/mt8167-clk.h>
#include <dt-bindings/memory/mt8167-larb-port.h>

#include "mt8167-pinfunc.h"

#include "mt8516.dtsi"

/ {
	compatible = "mediatek,mt8167";

	soc {
		topckgen: topckgen@10000000 {
			compatible = "mediatek,mt8167-topckgen", "syscon";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		infracfg: infracfg@10001000 {
			compatible = "mediatek,mt8167-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
		};

		apmixedsys: apmixedsys@10018000 {
			compatible = "mediatek,mt8167-apmixedsys", "syscon";
			reg = <0 0x10018000 0 0x710>;
			#clock-cells = <1>;
		};

		imgsys: syscon@15000000 {
			compatible = "mediatek,mt8167-imgsys", "syscon";
			reg = <0 0x15000000 0 0x1000>;
			#clock-cells = <1>;
		};

		vdecsys: syscon@16000000 {
			compatible = "mediatek,mt8167-vdecsys", "syscon";
			reg = <0 0x16000000 0 0x1000>;
			#clock-cells = <1>;
		};

		pio: pinctrl@1000b000 {
			compatible = "mediatek,mt8167-pinctrl";
			reg = <0 0x1000b000 0 0x1000>;
			mediatek,pctl-regmap = <&syscfg_pctl>;
			pins-are-numbered;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
		};
	};
};