// SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2018, Linaro Limited #include #include #include #include #include #include / { interrupt-parent = <&intc>; #address-cells = <2>; #size-cells = <2>; chosen { }; clocks { xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; }; sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; CPU0: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; power-domains = <&cpr>; power-domain-names = "cpr"; }; CPU1: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; power-domains = <&cpr>; power-domain-names = "cpr"; }; CPU2: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x102>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; power-domains = <&cpr>; power-domain-names = "cpr"; }; CPU3: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x103>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; clocks = <&apcs_glb>; operating-points-v2 = <&cpu_opp_table>; power-domains = <&cpr>; power-domain-names = "cpr"; }; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; idle-state-name = "standalone-power-collapse"; arm,psci-suspend-param = <0x40000003>; entry-latency-us = <125>; exit-latency-us = <180>; min-residency-us = <595>; local-timer-stop; }; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2-kryo-cpu"; opp-shared; opp-1094400000 { opp-hz = /bits/ 64 <1094400000>; required-opps = <&cpr_opp1>; }; opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; required-opps = <&cpr_opp2>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; required-opps = <&cpr_opp3>; }; }; cpr_opp_table: cpr-opp-table { compatible = "operating-points-v2-qcom-level"; cpr_opp1: opp1 { opp-level = <1>; qcom,opp-fuse-level = <1>; }; cpr_opp2: opp2 { opp-level = <2>; qcom,opp-fuse-level = <2>; }; cpr_opp3: opp3 { opp-level = <3>; qcom,opp-fuse-level = <3>; }; }; firmware { scm: scm { compatible = "qcom,scm-qcs404", "qcom,scm"; #reset-cells = <1>; }; }; memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ reg = <0 0x80000000 0 0>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; tz_apps_mem: memory@85900000 { reg = <0 0x85900000 0 0x500000>; no-map; }; xbl_mem: memory@85e00000 { reg = <0 0x85e00000 0 0x100000>; no-map; }; smem_region: memory@85f00000 { reg = <0 0x85f00000 0 0x200000>; no-map; }; tz_mem: memory@86100000 { reg = <0 0x86100000 0 0x300000>; no-map; }; wlan_fw_mem: memory@86400000 { reg = <0 0x86400000 0 0x1100000>; no-map; }; adsp_fw_mem: memory@87500000 { reg = <0 0x87500000 0 0x1a00000>; no-map; }; cdsp_fw_mem: memory@88f00000 { reg = <0 0x88f00000 0 0x600000>; no-map; }; wlan_msa_mem: memory@89500000 { reg = <0 0x89500000 0 0x100000>; no-map; }; uefi_mem: memory@9f800000 { reg = <0 0x9f800000 0 0x800000>; no-map; }; }; rpm-glink { compatible = "qcom,glink-rpm"; interrupts = ; qcom,rpm-msg-ram = <&rpm_msg_ram>; mboxes = <&apcs_glb 0>; rpm_requests: glink-channel { compatible = "qcom,rpm-qcs404"; qcom,glink-channels = "rpm_requests"; rpmcc: clock-controller { compatible = "qcom,rpmcc-qcs404"; #clock-cells = <1>; }; rpmpd: power-controller { compatible = "qcom,qcs404-rpmpd"; #power-domain-cells = <1>; operating-points-v2 = <&rpmpd_opp_table>; rpmpd_opp_table: opp-table { compatible = "operating-points-v2"; rpmpd_opp_ret: opp1 { opp-level = <16>; }; rpmpd_opp_ret_plus: opp2 { opp-level = <32>; }; rpmpd_opp_min_svs: opp3 { opp-level = <48>; }; rpmpd_opp_low_svs: opp4 { opp-level = <64>; }; rpmpd_opp_svs: opp5 { opp-level = <128>; }; rpmpd_opp_svs_plus: opp6 { opp-level = <192>; }; rpmpd_opp_nom: opp7 { opp-level = <256>; }; rpmpd_opp_nom_plus: opp8 { opp-level = <320>; }; rpmpd_opp_turbo: opp9 { opp-level = <384>; }; rpmpd_opp_turbo_no_cpr: opp10 { opp-level = <416>; }; rpmpd_opp_turbo_plus: opp11 { opp-level = <512>; }; }; }; }; }; smem { compatible = "qcom,smem"; memory-region = <&smem_region>; qcom,rpm-msg-ram = <&rpm_msg_ram>; hwlocks = <&tcsr_mutex 3>; }; tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_regs 0 0x1000>; #hwlock-cells = <1>; }; soc: soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; turingcc: clock-controller@800000 { compatible = "qcom,qcs404-turingcc"; reg = <0x00800000 0x30000>; clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; #clock-cells = <1>; #reset-cells = <1>; status = "disabled"; }; rpm_msg_ram: memory@60000 { compatible = "qcom,rpm-msg-ram"; reg = <0x00060000 0x6000>; }; qfprom: qfprom@a4000 { compatible = "qcom,qfprom"; reg = <0x000a4000 0x1000>; #address-cells = <1>; #size-cells = <1>; tsens_caldata: caldata@d0 { reg = <0x1f8 0x14>; }; cpr_efuse_speedbin: speedbin@13c { reg = <0x13c 0x4>; bits = <2 3>; }; cpr_efuse_quot_offset1: qoffset1@231 { reg = <0x231 0x4>; bits = <4 7>; }; cpr_efuse_quot_offset2: qoffset2@232 { reg = <0x232 0x4>; bits = <3 7>; }; cpr_efuse_quot_offset3: qoffset3@233 { reg = <0x233 0x4>; bits = <2 7>; }; cpr_efuse_init_voltage1: ivoltage1@229 { reg = <0x229 0x4>; bits = <4 6>; }; cpr_efuse_init_voltage2: ivoltage2@22a { reg = <0x22a 0x4>; bits = <2 6>; }; cpr_efuse_init_voltage3: ivoltage3@22b { reg = <0x22b 0x4>; bits = <0 6>; }; cpr_efuse_quot1: quot1@22b { reg = <0x22b 0x4>; bits = <6 12>; }; cpr_efuse_quot2: quot2@22d { reg = <0x22d 0x4>; bits = <2 12>; }; cpr_efuse_quot3: quot3@230 { reg = <0x230 0x4>; bits = <0 12>; }; cpr_efuse_ring1: ring1@228 { reg = <0x228 0x4>; bits = <0 3>; }; cpr_efuse_ring2: ring2@228 { reg = <0x228 0x4>; bits = <4 3>; }; cpr_efuse_ring3: ring3@229 { reg = <0x229 0x4>; bits = <0 3>; }; cpr_efuse_revision: revision@218 { reg = <0x218 0x4>; bits = <3 3>; }; }; rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; bimc: interconnect@400000 { reg = <0x00400000 0x80000>; compatible = "qcom,qcs404-bimc"; #interconnect-cells = <1>; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_BIMC_CLK>, <&rpmcc RPM_SMD_BIMC_A_CLK>; }; tsens: thermal-sensor@4a9000 { compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_caldata>; nvmem-cell-names = "calib"; #qcom,sensors = <10>; interrupts = ; interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; pcnoc: interconnect@500000 { reg = <0x00500000 0x15080>; compatible = "qcom,qcs404-pcnoc"; #interconnect-cells = <1>; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_PNOC_CLK>, <&rpmcc RPM_SMD_PNOC_A_CLK>; }; snoc: interconnect@580000 { reg = <0x00580000 0x23080>; compatible = "qcom,qcs404-snoc"; #interconnect-cells = <1>; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_SNOC_CLK>, <&rpmcc RPM_SMD_SNOC_A_CLK>; }; remoteproc_cdsp: remoteproc@b00000 { compatible = "qcom,qcs404-cdsp-pas"; reg = <0x00b00000 0x4040>; interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&xo_board>, <&gcc GCC_CDSP_CFG_AHB_CLK>, <&gcc GCC_CDSP_TBU_CLK>, <&gcc GCC_BIMC_CDSP_CLK>, <&turingcc TURING_WRAPPER_AON_CLK>, <&turingcc TURING_Q6SS_AHBS_AON_CLK>, <&turingcc TURING_Q6SS_AHBM_AON_CLK>, <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; clock-names = "xo", "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master", "q6_axim"; resets = <&gcc GCC_CDSP_RESTART>; reset-names = "restart"; qcom,halt-regs = <&tcsr 0x19004>; memory-region = <&cdsp_fw_mem>; qcom,smem-states = <&cdsp_smp2p_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts = ; qcom,remote-pid = <5>; mboxes = <&apcs_glb 12>; label = "cdsp"; }; }; tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>, <0x01300000 0x200000>, <0x07b00000 0x200000>; reg-names = "south", "north", "east"; interrupts = ; gpio-ranges = <&tlmm 0 0 120>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; blsp1_i2c0_default: blsp1-i2c0-default { pins = "gpio32", "gpio33"; function = "blsp_i2c0"; }; blsp1_i2c1_default: blsp1-i2c1-default { pins = "gpio24", "gpio25"; function = "blsp_i2c1"; }; blsp1_i2c2_default: blsp1-i2c2-default { sda { pins = "gpio19"; function = "blsp_i2c_sda_a2"; }; scl { pins = "gpio20"; function = "blsp_i2c_scl_a2"; }; }; blsp1_i2c3_default: blsp1-i2c3-default { pins = "gpio84", "gpio85"; function = "blsp_i2c3"; }; blsp1_i2c4_default: blsp1-i2c4-default { pins = "gpio117", "gpio118"; function = "blsp_i2c4"; }; blsp1_uart0_default: blsp1-uart0-default { pins = "gpio30", "gpio31", "gpio32", "gpio33"; function = "blsp_uart0"; }; blsp1_uart1_default: blsp1-uart1-default { pins = "gpio22", "gpio23"; function = "blsp_uart1"; }; blsp1_uart2_default: blsp1-uart2-default { rx { pins = "gpio18"; function = "blsp_uart_rx_a2"; }; tx { pins = "gpio17"; function = "blsp_uart_tx_a2"; }; }; blsp1_uart3_default: blsp1-uart3-default { pins = "gpio82", "gpio83", "gpio84", "gpio85"; function = "blsp_uart3"; }; blsp2_i2c0_default: blsp2-i2c0-default { pins = "gpio28", "gpio29"; function = "blsp_i2c5"; }; blsp1_spi0_default: blsp1-spi0-default { pins = "gpio30", "gpio31", "gpio32", "gpio33"; function = "blsp_spi0"; }; blsp1_spi1_default: blsp1-spi1-default { pins = "gpio22", "gpio23", "gpio24", "gpio25"; function = "blsp_spi1"; }; blsp1_spi2_default: blsp1-spi2-default { pins = "gpio17", "gpio18", "gpio19", "gpio20"; function = "blsp_spi2"; }; blsp1_spi3_default: blsp1-spi3-default { pins = "gpio82", "gpio83", "gpio84", "gpio85"; function = "blsp_spi3"; }; blsp1_spi4_default: blsp1-spi4-default { pins = "gpio37", "gpio38", "gpio117", "gpio118"; function = "blsp_spi4"; }; blsp2_spi0_default: blsp2-spi0-default { pins = "gpio26", "gpio27", "gpio28", "gpio29"; function = "blsp_spi5"; }; blsp2_uart0_default: blsp2-uart0-default { pins = "gpio26", "gpio27", "gpio28", "gpio29"; function = "blsp_uart5"; }; }; gcc: clock-controller@1800000 { compatible = "qcom,gcc-qcs404"; reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; }; tcsr_mutex_regs: syscon@1905000 { compatible = "syscon"; reg = <0x01905000 0x20000>; }; tcsr: syscon@1937000 { compatible = "syscon"; reg = <0x01937000 0x25000>; }; spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x001000>, <0x02400000 0x800000>, <0x02c00000 0x800000>, <0x03800000 0x200000>, <0x0200a000 0x002100>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; }; remoteproc_wcss: remoteproc@7400000 { compatible = "qcom,qcs404-wcss-pas"; reg = <0x07400000 0x4040>; interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&xo_board>; clock-names = "xo"; memory-region = <&wlan_fw_mem>; qcom,smem-states = <&wcss_smp2p_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts = ; qcom,remote-pid = <1>; mboxes = <&apcs_glb 16>; label = "wcss"; }; }; pcie_phy: phy@7786000 { compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; reg = <0x07786000 0xb8>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, <&gcc 21>; reset-names = "phy", "pipe"; clock-output-names = "pcie_0_pipe_clk"; #phy-cells = <0>; status = "disabled"; }; sdcc1: sdcc@7804000 { compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x7805000 0x1000>; reg-names = "hc", "cqhci"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, <&xo_board>; clock-names = "core", "iface", "xo"; status = "disabled"; }; blsp1_dma: dma@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07884000 0x25000>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <0>; status = "okay"; }; blsp1_uart0: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078af000 0x200>; interrupts = ; clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; dmas = <&blsp1_dma 1>, <&blsp1_dma 0>; dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart0_default>; status = "disabled"; }; blsp1_uart1: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b0000 0x200>; interrupts = ; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; dmas = <&blsp1_dma 3>, <&blsp1_dma 2>; dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart1_default>; status = "disabled"; }; blsp1_uart2: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b1000 0x200>; interrupts = ; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; dmas = <&blsp1_dma 5>, <&blsp1_dma 4>; dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart2_default>; status = "okay"; }; ethernet: ethernet@7a80000 { compatible = "qcom,qcs404-ethqos"; reg = <0x07a80000 0x10000>, <0x07a96000 0x100>; reg-names = "stmmaceth", "rgmii"; clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; clocks = <&gcc GCC_ETH_AXI_CLK>, <&gcc GCC_ETH_SLAVE_AHB_CLK>, <&gcc GCC_ETH_PTP_CLK>, <&gcc GCC_ETH_RGMII_CLK>; interrupts = , ; interrupt-names = "macirq", "eth_lpi"; snps,tso; rx-fifo-depth = <4096>; tx-fifo-depth = <4096>; status = "disabled"; }; wifi: wifi@a000000 { compatible = "qcom,wcn3990-wifi"; reg = <0xa000000 0x800000>; reg-names = "membase"; memory-region = <&wlan_msa_mem>; interrupts = , , , , , , , , , , , ; status = "disabled"; }; blsp1_uart3: serial@78b2000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078b2000 0x200>; interrupts = ; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; dmas = <&blsp1_dma 7>, <&blsp1_dma 6>; dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart3_default>; status = "disabled"; }; blsp1_i2c0: i2c@78b5000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b5000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c0_default>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; blsp1_spi0: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b5000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi0_default>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; blsp1_i2c1: i2c@78b6000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b6000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c1_default>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; blsp1_spi1: spi@78b6000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b6000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi1_default>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; blsp1_i2c2: i2c@78b7000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b7000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c2_default>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; blsp1_spi2: spi@78b7000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b7000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi2_default>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; blsp1_i2c3: i2c@78b8000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b8000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c3_default>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; blsp1_spi3: spi@78b8000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b8000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi3_default>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; blsp1_i2c4: i2c@78b9000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b9000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c4_default>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; blsp1_spi4: spi@78b9000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b9000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi4_default>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; blsp2_dma: dma@7ac4000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07ac4000 0x17000>; interrupts = ; clocks = <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <0>; status = "disabled"; }; blsp2_uart0: serial@7aef000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x07aef000 0x200>; interrupts = ; clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; dmas = <&blsp2_dma 1>, <&blsp2_dma 0>; dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_uart0_default>; status = "disabled"; }; blsp2_i2c0: i2c@7af5000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07af5000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP2_AHB_CLK>, <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_i2c0_default>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; blsp2_spi0: spi@7af5000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x07af5000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP2_AHB_CLK>, <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; clock-names = "iface", "core"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_spi0_default>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; #interrupt-cells = <3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; }; apcs_glb: mailbox@b011000 { compatible = "qcom,qcs404-apcs-apps-global", "syscon"; reg = <0x0b011000 0x1000>; #mbox-cells = <1>; clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; clock-names = "pll", "aux"; #clock-cells = <0>; }; apcs_hfpll: clock-controller@b016000 { compatible = "qcom,hfpll"; reg = <0x0b016000 0x30>; #clock-cells = <0>; clock-output-names = "apcs_hfpll"; clocks = <&xo_board>; clock-names = "xo"; }; watchdog@b017000 { compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; reg = <0x0b017000 0x1000>; clocks = <&sleep_clk>; }; cpr: power-controller@b018000 { compatible = "qcom,qcs404-cpr", "qcom,cpr"; reg = <0x0b018000 0x1000>; interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; clocks = <&xo_board>; clock-names = "ref"; vdd-apc-supply = <&pms405_s3>; #power-domain-cells = <0>; operating-points-v2 = <&cpr_opp_table>; acc-syscon = <&tcsr>; nvmem-cells = <&cpr_efuse_quot_offset1>, <&cpr_efuse_quot_offset2>, <&cpr_efuse_quot_offset3>, <&cpr_efuse_init_voltage1>, <&cpr_efuse_init_voltage2>, <&cpr_efuse_init_voltage3>, <&cpr_efuse_quot1>, <&cpr_efuse_quot2>, <&cpr_efuse_quot3>, <&cpr_efuse_ring1>, <&cpr_efuse_ring2>, <&cpr_efuse_ring3>, <&cpr_efuse_revision>; nvmem-cell-names = "cpr_quotient_offset1", "cpr_quotient_offset2", "cpr_quotient_offset3", "cpr_init_voltage1", "cpr_init_voltage2", "cpr_init_voltage3", "cpr_quotient1", "cpr_quotient2", "cpr_quotient3", "cpr_ring_osc1", "cpr_ring_osc2", "cpr_ring_osc3", "cpr_fuse_revision"; }; timer@b120000 { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "arm,armv7-timer-mem"; reg = <0x0b120000 0x1000>; clock-frequency = <19200000>; frame@b121000 { frame-number = <0>; interrupts = , ; reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>; }; frame@b123000 { frame-number = <1>; interrupts = ; reg = <0x0b123000 0x1000>; status = "disabled"; }; frame@b124000 { frame-number = <2>; interrupts = ; reg = <0x0b124000 0x1000>; status = "disabled"; }; frame@b125000 { frame-number = <3>; interrupts = ; reg = <0x0b125000 0x1000>; status = "disabled"; }; frame@b126000 { frame-number = <4>; interrupts = ; reg = <0x0b126000 0x1000>; status = "disabled"; }; frame@b127000 { frame-number = <5>; interrupts = ; reg = <0xb127000 0x1000>; status = "disabled"; }; frame@b128000 { frame-number = <6>; interrupts = ; reg = <0x0b128000 0x1000>; status = "disabled"; }; }; remoteproc_adsp: remoteproc@c700000 { compatible = "qcom,qcs404-adsp-pas"; reg = <0x0c700000 0x4040>; interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&xo_board>; clock-names = "xo"; memory-region = <&adsp_fw_mem>; qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts = ; qcom,remote-pid = <2>; mboxes = <&apcs_glb 8>; label = "adsp"; }; }; pcie: pci@10000000 { compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; reg = <0x10000000 0xf1d>, <0x10000f20 0xa8>, <0x07780000 0x2000>, <0x10001000 0x2000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; num-lanes = <1>; #address-cells = <3>; #size-cells = <2>; ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>; clock-names = "iface", "aux", "master_bus", "slave_bus"; resets = <&gcc 18>, <&gcc 17>, <&gcc 15>, <&gcc 19>, <&gcc GCC_PCIE_0_BCR>, <&gcc 16>; reset-names = "axi_m", "axi_s", "axi_m_sticky", "pipe_sticky", "pwr", "ahb"; phys = <&pcie_phy>; phy-names = "pciephy"; status = "disabled"; }; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , ; }; smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupts = ; mboxes = <&apcs_glb 10>; qcom,local-pid = <0>; qcom,remote-pid = <2>; adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupts = ; mboxes = <&apcs_glb 14>; qcom,local-pid = <0>; qcom,remote-pid = <5>; cdsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; cdsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-wcss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupts = ; mboxes = <&apcs_glb 18>; qcom,local-pid = <0>; qcom,remote-pid = <1>; wcss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; wcss_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; thermal-zones { aoss-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens 0>; trips { aoss_alert0: trip-point0 { temperature = <105000>; hysteresis = <2000>; type = "hot"; }; }; }; q6-hvx-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens 1>; trips { q6_hvx_alert0: trip-point0 { temperature = <105000>; hysteresis = <2000>; type = "hot"; }; }; }; lpass-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens 2>; trips { lpass_alert0: trip-point0 { temperature = <105000>; hysteresis = <2000>; type = "hot"; }; }; }; wlan-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens 3>; trips { wlan_alert0: trip-point0 { temperature = <105000>; hysteresis = <2000>; type = "hot"; }; }; }; cluster-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens 4>; trips { cluster_alert0: trip-point0 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cluster_alert1: trip-point1 { temperature = <105000>; hysteresis = <2000>; type = "passive"; }; cluster_crit: cluster_crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cluster_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu0-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens 5>; trips { cpu0_alert0: trip-point0 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cpu0_alert1: trip-point1 { temperature = <105000>; hysteresis = <2000>; type = "passive"; }; cpu0_crit: cpu_crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu0_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens 6>; trips { cpu1_alert0: trip-point0 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cpu1_alert1: trip-point1 { temperature = <105000>; hysteresis = <2000>; type = "passive"; }; cpu1_crit: cpu_crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu1_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens 7>; trips { cpu2_alert0: trip-point0 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cpu2_alert1: trip-point1 { temperature = <105000>; hysteresis = <2000>; type = "passive"; }; cpu2_crit: cpu_crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu2_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens 8>; trips { cpu3_alert0: trip-point0 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; cpu3_alert1: trip-point1 { temperature = <105000>; hysteresis = <2000>; type = "passive"; }; cpu3_crit: cpu_crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu3_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; gpu-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsens 9>; trips { gpu_alert0: trip-point0 { temperature = <95000>; hysteresis = <2000>; type = "hot"; }; }; }; }; };