// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for AM6 SoC Family Main Domain peripherals
 *
 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
 */
#include <dt-bindings/phy/phy-am654-serdes.h>

&cbass_main {
	msmc_ram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x0 0x70000000 0x0 0x200000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x70000000 0x200000>;

		atf-sram@0 {
			reg = <0x0 0x20000>;
		};

		sysfw-sram@f0000 {
			reg = <0xf0000 0x10000>;
		};

		l3cache-sram@100000 {
			reg = <0x100000 0x100000>;
		};
	};

	gic500: interrupt-controller@1800000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
		      <0x00 0x01880000 0x00 0x90000>;	/* GICR */
		/*
		 * vcpumntirq:
		 * virtual CPU interface maintenance interrupt
		 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		gic_its: msi-controller@1820000 {
			compatible = "arm,gic-v3-its";
			reg = <0x00 0x01820000 0x00 0x10000>;
			socionext,synquacer-pre-its = <0x1000000 0x400000>;
			msi-controller;
			#msi-cells = <1>;
		};
	};

	serdes0: serdes@900000 {
		compatible = "ti,phy-am654-serdes";
		reg = <0x0 0x900000 0x0 0x2000>;
		reg-names = "serdes";
		#phy-cells = <2>;
		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
		clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
		assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
		assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
		ti,serdes-clk = <&serdes0_clk>;
		#clock-cells = <1>;
		mux-controls = <&serdes_mux 0>;
	};

	serdes1: serdes@910000 {
		compatible = "ti,phy-am654-serdes";
		reg = <0x0 0x910000 0x0 0x2000>;
		reg-names = "serdes";
		#phy-cells = <2>;
		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
		clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
		assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
		assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
		ti,serdes-clk = <&serdes1_clk>;
		#clock-cells = <1>;
		mux-controls = <&serdes_mux 1>;
	};

	main_uart0: serial@2800000 {
		compatible = "ti,am654-uart";
		reg = <0x00 0x02800000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart1: serial@2810000 {
		compatible = "ti,am654-uart";
		reg = <0x00 0x02810000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart2: serial@2820000 {
		compatible = "ti,am654-uart";
		reg = <0x00 0x02820000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
	};

	crypto: crypto@4e00000 {
		compatible = "ti,am654-sa2ul";
		reg = <0x0 0x4e00000 0x0 0x1200>;
		power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;

		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
				<&main_udmap 0x4001>;
		dma-names = "tx", "rx1", "rx2";
		dma-coherent;

		rng: rng@4e10000 {
			compatible = "inside-secure,safexcel-eip76";
			reg = <0x0 0x4e10000 0x0 0x7d>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&k3_clks 136 1>;
		};
	};

	main_pmx0: pinctrl@11c000 {
		compatible = "pinctrl-single";
		reg = <0x0 0x11c000 0x0 0x2e4>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	main_pmx1: pinctrl@11c2e8 {
		compatible = "pinctrl-single";
		reg = <0x0 0x11c2e8 0x0 0x24>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	main_i2c0: i2c@2000000 {
		compatible = "ti,am654-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2000000 0x0 0x100>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 110 1>;
		power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c1: i2c@2010000 {
		compatible = "ti,am654-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2010000 0x0 0x100>;
		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 111 1>;
		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c2: i2c@2020000 {
		compatible = "ti,am654-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2020000 0x0 0x100>;
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 112 1>;
		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c3: i2c@2030000 {
		compatible = "ti,am654-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2030000 0x0 0x100>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 113 1>;
		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
	};

	ecap0: pwm@3100000 {
		compatible = "ti,am654-ecap", "ti,am3352-ecap";
		#pwm-cells = <3>;
		reg = <0x0 0x03100000 0x0 0x60>;
		power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 39 0>;
		clock-names = "fck";
	};

	main_spi0: spi@2100000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2100000 0x0 0x400>;
		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 137 1>;
		power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
		dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
		dma-names = "tx0", "rx0";
	};

	main_spi1: spi@2110000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2110000 0x0 0x400>;
		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 138 1>;
		power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
		assigned-clocks = <&k3_clks 137 1>;
		assigned-clock-rates = <48000000>;
	};

	main_spi2: spi@2120000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2120000 0x0 0x400>;
		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 139 1>;
		power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	main_spi3: spi@2130000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2130000 0x0 0x400>;
		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 140 1>;
		power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	main_spi4: spi@2140000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2140000 0x0 0x400>;
		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 141 1>;
		power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	sdhci0: sdhci@4f80000 {
		compatible = "ti,am654-sdhci-5.1";
		reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
		power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
		clock-names = "clk_ahb", "clk_xin";
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		mmc-ddr-1_8v;
		mmc-hs200-1_8v;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-mmc-hs = <0x0>;
		ti,otap-del-sel-sd-hs = <0x0>;
		ti,otap-del-sel-sdr12 = <0x0>;
		ti,otap-del-sel-sdr25 = <0x0>;
		ti,otap-del-sel-sdr50 = <0x8>;
		ti,otap-del-sel-sdr104 = <0x7>;
		ti,otap-del-sel-ddr50 = <0x5>;
		ti,otap-del-sel-ddr52 = <0x5>;
		ti,otap-del-sel-hs200 = <0x5>;
		ti,otap-del-sel-hs400 = <0x0>;
		ti,trm-icp = <0x8>;
		dma-coherent;
	};

	sdhci1: sdhci@4fa0000 {
		compatible = "ti,am654-sdhci-5.1";
		reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
		power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
		clock-names = "clk_ahb", "clk_xin";
		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-mmc-hs = <0x0>;
		ti,otap-del-sel-sd-hs = <0x0>;
		ti,otap-del-sel-sdr12 = <0x0>;
		ti,otap-del-sel-sdr25 = <0x0>;
		ti,otap-del-sel-sdr50 = <0x8>;
		ti,otap-del-sel-sdr104 = <0x7>;
		ti,otap-del-sel-ddr50 = <0x4>;
		ti,otap-del-sel-ddr52 = <0x4>;
		ti,otap-del-sel-hs200 = <0x7>;
		ti,clkbuf-sel = <0x7>;
		ti,otap-del-sel = <0x2>;
		ti,trm-icp = <0x8>;
		dma-coherent;
		no-1-8-v;
	};

	scm_conf: scm-conf@100000 {
		compatible = "syscon", "simple-mfd";
		reg = <0 0x00100000 0 0x1c000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x00100000 0x1c000>;

		pcie0_mode: pcie-mode@4060 {
			compatible = "syscon";
			reg = <0x00004060 0x4>;
		};

		pcie1_mode: pcie-mode@4070 {
			compatible = "syscon";
			reg = <0x00004070 0x4>;
		};

		pcie_devid: pcie-devid@210 {
			compatible = "syscon";
			reg = <0x00000210 0x4>;
		};

		serdes0_clk: clock@4080 {
			compatible = "syscon";
			reg = <0x00004080 0x4>;
		};

		serdes1_clk: clock@4090 {
			compatible = "syscon";
			reg = <0x00004090 0x4>;
		};

		serdes_mux: mux-controller {
			compatible = "mmio-mux";
			#mux-control-cells = <1>;
			mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
					<0x4090 0x3>; /* SERDES1 lane select */
		};

		dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
			compatible = "syscon";
			reg = <0x0000041e0 0x14>;
		};

		ehrpwm_tbclk: clock@4140 {
			compatible = "ti,am654-ehrpwm-tbclk", "syscon";
			reg = <0x4140 0x18>;
			#clock-cells = <1>;
		};
	};

	dwc3_0: dwc3@4000000 {
		compatible = "ti,am654-dwc3";
		reg = <0x0 0x4000000 0x0 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x4000000 0x20000>;
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		dma-coherent;
		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
		assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
		assigned-clock-parents = <&k3_clks 151 4>,	/* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
					 <&k3_clks 151 9>;	/* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */

		usb0: usb@10000 {
			compatible = "snps,dwc3";
			reg = <0x10000 0x10000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "peripheral",
					  "host",
					  "otg";
			maximum-speed = "high-speed";
			dr_mode = "otg";
			phys = <&usb0_phy>;
			phy-names = "usb2-phy";
			snps,dis_u3_susphy_quirk;
		};
	};

	usb0_phy: phy@4100000 {
		compatible = "ti,am654-usb2", "ti,omap-usb2";
		reg = <0x0 0x4100000 0x0 0x54>;
		syscon-phy-power = <&scm_conf 0x4000>;
		clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
		clock-names = "wkupclk", "refclk";
		#phy-cells = <0>;
	};

	dwc3_1: dwc3@4020000 {
		compatible = "ti,am654-dwc3";
		reg = <0x0 0x4020000 0x0 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x4020000 0x20000>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		dma-coherent;
		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 152 2>;
		assigned-clocks = <&k3_clks 152 2>;
		assigned-clock-parents = <&k3_clks 152 4>;	/* set REF_CLK to 20MHz i.e. PER0_PLL/48 */

		usb1: usb@10000 {
			compatible = "snps,dwc3";
			reg = <0x10000 0x10000>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "peripheral",
					  "host",
					  "otg";
			maximum-speed = "high-speed";
			dr_mode = "otg";
			phys = <&usb1_phy>;
			phy-names = "usb2-phy";
		};
	};

	usb1_phy: phy@4110000 {
		compatible = "ti,am654-usb2", "ti,omap-usb2";
		reg = <0x0 0x4110000 0x0 0x54>;
		syscon-phy-power = <&scm_conf 0x4020>;
		clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
		clock-names = "wkupclk", "refclk";
		#phy-cells = <0>;
	};

	intr_main_gpio: interrupt-controller0 {
		compatible = "ti,sci-intr";
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <100>;
		ti,interrupt-ranges = <0 392 32>;
	};

	main-navss {
		compatible = "simple-mfd";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-coherent;
		dma-ranges;

		ti,sci-dev-id = <118>;

		intr_main_navss: interrupt-controller1 {
			compatible = "ti,sci-intr";
			ti,intr-trigger-type = <4>;
			interrupt-controller;
			interrupt-parent = <&gic500>;
			#interrupt-cells = <1>;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <182>;
			ti,interrupt-ranges = <0 64 64>,
					      <64 448 64>;
		};

		inta_main_udmass: interrupt-controller@33d00000 {
			compatible = "ti,sci-inta";
			reg = <0x0 0x33d00000 0x0 0x100000>;
			interrupt-controller;
			interrupt-parent = <&intr_main_navss>;
			msi-controller;
			#interrupt-cells = <0>;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <179>;
			ti,interrupt-ranges = <0 0 256>;
		};

		secure_proxy_main: mailbox@32c00000 {
			compatible = "ti,am654-secure-proxy";
			#mbox-cells = <1>;
			reg-names = "target_data", "rt", "scfg";
			reg = <0x00 0x32c00000 0x00 0x100000>,
			      <0x00 0x32400000 0x00 0x100000>,
			      <0x00 0x32800000 0x00 0x100000>;
			interrupt-names = "rx_011";
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		};

		hwspinlock: spinlock@30e00000 {
			compatible = "ti,am654-hwspinlock";
			reg = <0x00 0x30e00000 0x00 0x1000>;
			#hwlock-cells = <1>;
		};

		mailbox0_cluster0: mailbox@31f80000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f80000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster1: mailbox@31f81000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f81000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster2: mailbox@31f82000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f82000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster3: mailbox@31f83000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f83000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster4: mailbox@31f84000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f84000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster5: mailbox@31f85000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f85000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster6: mailbox@31f86000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f86000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster7: mailbox@31f87000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f87000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster8: mailbox@31f88000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f88000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster9: mailbox@31f89000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f89000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster10: mailbox@31f8a000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8a000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster11: mailbox@31f8b000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8b000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		ringacc: ringacc@3c000000 {
			compatible = "ti,am654-navss-ringacc";
			reg =	<0x0 0x3c000000 0x0 0x400000>,
				<0x0 0x38000000 0x0 0x400000>,
				<0x0 0x31120000 0x0 0x100>,
				<0x0 0x33000000 0x0 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
			ti,num-rings = <818>;
			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <187>;
			msi-parent = <&inta_main_udmass>;
		};

		main_udmap: dma-controller@31150000 {
			compatible = "ti,am654-navss-main-udmap";
			reg =	<0x0 0x31150000 0x0 0x100>,
				<0x0 0x34000000 0x0 0x100000>,
				<0x0 0x35000000 0x0 0x100000>;
			reg-names = "gcfg", "rchanrt", "tchanrt";
			msi-parent = <&inta_main_udmass>;
			#dma-cells = <1>;

			ti,sci = <&dmsc>;
			ti,sci-dev-id = <188>;
			ti,ringacc = <&ringacc>;

			ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
						<0xd>; /* TX_CHAN */
			ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
						<0xa>; /* RX_CHAN */
			ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
		};

		cpts@310d0000 {
			compatible = "ti,am65-cpts";
			reg = <0x0 0x310d0000 0x0 0x400>;
			reg-names = "cpts";
			clocks = <&main_cpts_mux>;
			clock-names = "cpts";
			interrupts-extended = <&intr_main_navss 391>;
			interrupt-names = "cpts";
			ti,cpts-periodic-outputs = <6>;
			ti,cpts-ext-ts-inputs = <8>;

			main_cpts_mux: refclk-mux {
				#clock-cells = <0>;
				clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
					<&k3_clks 118 6>, <&k3_clks 118 3>,
					<&k3_clks 118 8>, <&k3_clks 118 14>,
					<&k3_clks 120 3>, <&k3_clks 121 3>;
				assigned-clocks = <&main_cpts_mux>;
				assigned-clock-parents = <&k3_clks 118 5>;
			};
		};
	};

	main_gpio0: gpio@600000 {
		compatible = "ti,am654-gpio", "ti,keystone-gpio";
		reg = <0x0 0x600000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&intr_main_gpio>;
		interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <96>;
		ti,davinci-gpio-unbanked = <0>;
		clocks = <&k3_clks 57 0>;
		clock-names = "gpio";
	};

	main_gpio1: gpio@601000 {
		compatible = "ti,am654-gpio", "ti,keystone-gpio";
		reg = <0x0 0x601000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&intr_main_gpio>;
		interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <90>;
		ti,davinci-gpio-unbanked = <0>;
		clocks = <&k3_clks 58 0>;
		clock-names = "gpio";
	};

	pcie0_rc: pcie@5500000 {
		compatible = "ti,am654-pcie-rc";
		reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
		reg-names = "app", "dbics", "config", "atu";
		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000
			  0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
		ti,syscon-pcie-id = <&pcie_devid>;
		ti,syscon-pcie-mode = <&pcie0_mode>;
		bus-range = <0x0 0xff>;
		num-viewport = <16>;
		max-link-speed = <2>;
		dma-coherent;
		interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
		msi-map = <0x0 &gic_its 0x0 0x10000>;
	};

	pcie0_ep: pcie-ep@5500000 {
		compatible = "ti,am654-pcie-ep";
		reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
		reg-names = "app", "dbics", "addr_space", "atu";
		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
		ti,syscon-pcie-mode = <&pcie0_mode>;
		num-ib-windows = <16>;
		num-ob-windows = <16>;
		max-link-speed = <2>;
		dma-coherent;
		interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
	};

	pcie1_rc: pcie@5600000 {
		compatible = "ti,am654-pcie-rc";
		reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
		reg-names = "app", "dbics", "config", "atu";
		power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
			  0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
		ti,syscon-pcie-id = <&pcie_devid>;
		ti,syscon-pcie-mode = <&pcie1_mode>;
		bus-range = <0x0 0xff>;
		num-viewport = <16>;
		max-link-speed = <2>;
		dma-coherent;
		interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
		msi-map = <0x0 &gic_its 0x10000 0x10000>;
	};

	pcie1_ep: pcie-ep@5600000 {
		compatible = "ti,am654-pcie-ep";
		reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
		reg-names = "app", "dbics", "addr_space", "atu";
		power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
		ti,syscon-pcie-mode = <&pcie1_mode>;
		num-ib-windows = <16>;
		num-ob-windows = <16>;
		max-link-speed = <2>;
		dma-coherent;
		interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
	};

	mcasp0: mcasp@2b00000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b00000 0x0 0x2000>,
			<0x0 0x02b08000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 104 0>;
		clock-names = "fck";
		power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp1: mcasp@2b10000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b10000 0x0 0x2000>,
			<0x0 0x02b18000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 105 0>;
		clock-names = "fck";
		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
	};

	mcasp2: mcasp@2b20000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b20000 0x0 0x2000>,
			<0x0 0x02b28000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 106 0>;
		clock-names = "fck";
		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
	};

	cal: cal@6f03000 {
		compatible = "ti,am654-cal";
		reg = <0x0 0x06f03000 0x0 0x400>,
		      <0x0 0x06f03800 0x0 0x40>;
		reg-names = "cal_top",
			    "cal_rx_core0";
		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
		ti,camerrx-control = <&scm_conf 0x40c0>;
		clock-names = "fck";
		clocks = <&k3_clks 2 0>;
		power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			csi2_0: port@0 {
				reg = <0>;
			};
		};
	};

	dss: dss@4a00000 {
		compatible = "ti,am65x-dss";
		reg =	<0x0 0x04a00000 0x0 0x1000>, /* common */
			<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
			<0x0 0x04a06000 0x0 0x1000>, /* vid */
			<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
			<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
			<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
			<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
		reg-names = "common", "vidl1", "vid",
			"ovr1", "ovr2", "vp1", "vp2";

		ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;

		power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;

		clocks =	<&k3_clks 67 1>,
				<&k3_clks 216 1>,
				<&k3_clks 67 2>;
		clock-names = "fck", "vp1", "vp2";

		/*
		 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
		 * DIV1. See "Figure 12-3365. DSS Integration"
		 * in AM65x TRM for details.
		 */
		assigned-clocks = <&k3_clks 67 2>;
		assigned-clock-parents = <&k3_clks 67 5>;

		interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;

		dma-coherent;

		dss_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	ehrpwm0: pwm@3000000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3000000 0x0 0x100>;
		power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
		clock-names = "tbclk", "fck";
	};

	ehrpwm1: pwm@3010000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3010000 0x0 0x100>;
		power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
		clock-names = "tbclk", "fck";
	};

	ehrpwm2: pwm@3020000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3020000 0x0 0x100>;
		power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
		clock-names = "tbclk", "fck";
	};

	ehrpwm3: pwm@3030000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3030000 0x0 0x100>;
		power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
		clock-names = "tbclk", "fck";
	};

	ehrpwm4: pwm@3040000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3040000 0x0 0x100>;
		power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
		clock-names = "tbclk", "fck";
	};

	ehrpwm5: pwm@3050000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3050000 0x0 0x100>;
		power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
		clock-names = "tbclk", "fck";
	};
};