/* * B4420DS Device Tree Source * * Copyright 2012 - 2015 Freescale Semiconductor, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * This software is provided by Freescale Semiconductor "as is" and any * express or implied warranties, including, but not limited to, the implied * warranties of merchantability and fitness for a particular purpose are * disclaimed. In no event shall Freescale Semiconductor be liable for any * direct, indirect, incidental, special, exemplary, or consequential damages * (including, but not limited to, procurement of substitute goods or services; * loss of use, data, or profits; or business interruption) however caused and * on any theory of liability, whether in contract, strict liability, or tort * (including negligence or otherwise) arising in any way out of the use of * this software, even if advised of the possibility of such damage. */ / { model = "fsl,B4QDS"; compatible = "fsl,B4QDS"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; aliases { crypto = &crypto; phy_sgmii_10 = &phy_sgmii_10; phy_sgmii_11 = &phy_sgmii_11; phy_sgmii_1c = &phy_sgmii_1c; phy_sgmii_1d = &phy_sgmii_1d; }; ifc: localbus@ffe124000 { reg = <0xf 0xfe124000 0 0x2000>; ranges = <0 0 0xf 0xe8000000 0x08000000 2 0 0xf 0xff800000 0x00010000 3 0 0xf 0xffdf0000 0x00008000>; nor@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; reg = <0x0 0x0 0x8000000>; bank-width = <2>; device-width = <1>; }; nand@2,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,ifc-nand"; reg = <0x2 0x0 0x10000>; partition@0 { /* This location must not be altered */ /* 1MB for u-boot Bootloader Image */ reg = <0x0 0x00100000>; label = "NAND U-Boot Image"; read-only; }; partition@100000 { /* 1MB for DTB Image */ reg = <0x00100000 0x00100000>; label = "NAND DTB Image"; }; partition@200000 { /* 10MB for Linux Kernel Image */ reg = <0x00200000 0x00A00000>; label = "NAND Linux Kernel Image"; }; partition@c00000 { /* 500MB for Root file System Image */ reg = <0x00c00000 0x1F400000>; label = "NAND RFS Image"; }; }; board-control@3,0 { compatible = "fsl,b4qds-fpga", "fsl,fpga-qixis"; reg = <3 0 0x300>; }; }; memory { device_type = "memory"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; bman_fbpr: bman-fbpr { size = <0 0x1000000>; alignment = <0 0x1000000>; }; qman_fqd: qman-fqd { size = <0 0x400000>; alignment = <0 0x400000>; }; qman_pfdr: qman-pfdr { size = <0 0x2000000>; alignment = <0 0x2000000>; }; }; dcsr: dcsr@f00000000 { ranges = <0x00000000 0xf 0x00000000 0x01052000>; }; bportals: bman-portals@ff4000000 { ranges = <0x0 0xf 0xf4000000 0x2000000>; }; qportals: qman-portals@ff6000000 { ranges = <0x0 0xf 0xf6000000 0x2000000>; }; soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; spi@110000 { flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25wf040", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; /* input clock */ }; }; sdhc@114000 { /*Disabled as there is no sdhc connector on B4420QDS board*/ status = "disabled"; }; i2c@118000 { mux@77 { compatible = "nxp,pca9547"; reg = <0x77>; #address-cells = <1>; #size-cells = <0>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; }; eeprom@51 { compatible = "atmel,24c256"; reg = <0x51>; }; eeprom@53 { compatible = "atmel,24c256"; reg = <0x53>; }; eeprom@57 { compatible = "atmel,24c256"; reg = <0x57>; }; rtc@68 { compatible = "dallas,ds3232"; reg = <0x68>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <0x2>; ina220@40 { compatible = "ti,ina220"; reg = <0x40>; shunt-resistor = <1000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <0x3>; adt7461@4c { compatible = "adi,adt7461"; reg = <0x4c>; }; }; }; }; usb@210000 { dr_mode = "host"; phy_type = "ulpi"; }; fman@400000 { ethernet@e0000 { phy-handle = <&phy_sgmii_10>; phy-connection-type = "sgmii"; }; ethernet@e2000 { phy-handle = <&phy_sgmii_11>; phy-connection-type = "sgmii"; }; ethernet@e4000 { phy-handle = <&phy_sgmii_1c>; phy-connection-type = "sgmii"; }; ethernet@e6000 { phy-handle = <&phy_sgmii_1d>; phy-connection-type = "sgmii"; }; mdio@fc000 { phy_sgmii_10: ethernet-phy@10 { reg = <0x10>; }; phy_sgmii_11: ethernet-phy@11 { reg = <0x11>; }; phy_sgmii_1c: ethernet-phy@1c { reg = <0x1c>; status = "disabled"; }; phy_sgmii_1d: ethernet-phy@1d { reg = <0x1d>; status = "disabled"; }; }; }; }; pci0: pcie@ffe200000 { reg = <0xf 0xfe200000 0 0x10000>; ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x20000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; }; /include/ "b4si-post.dtsi"