// SPDX-License-Identifier: GPL-2.0-or-later /* * MPC8572 DS Core1 Device Tree Source in CAMP mode. * * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache * can be shared, all the other devices must be assigned to one core only. * This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi. * * Please note to add "-b 1" for core1's dts compiling. * * Copyright 2007-2009 Freescale Semiconductor Inc. */ /include/ "mpc8572ds.dts" / { model = "fsl,MPC8572DS"; compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP"; cpus { PowerPC,8572@0 { status = "disabled"; }; PowerPC,8572@1 { }; }; localbus@ffe05000 { status = "disabled"; }; soc8572@ffe00000 { ecm-law@0 { status = "disabled"; }; ecm@1000 { status = "disabled"; }; memory-controller@2000 { status = "disabled"; }; memory-controller@6000 { status = "disabled"; }; i2c@3000 { status = "disabled"; }; i2c@3100 { status = "disabled"; }; serial@4500 { status = "disabled"; }; gpio-controller@f000 { status = "disabled"; }; l2-cache-controller@20000 { cache-size = <0x80000>; // L2, 512K }; dma@21300 { status = "disabled"; }; ethernet@24000 { status = "disabled"; }; ptp_clock@24e00 { status = "disabled"; }; ethernet@25000 { status = "disabled"; }; mdio@25520 { status = "disabled"; }; crypto@30000 { status = "disabled"; }; pic@40000 { protected-sources = < 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */ 29 30 34 35 36 40 /* enet0 enet1 */ 24 25 20 21 22 23 /* pci0 pci1 dma1 */ 43 /* i2c */ 0x1 0x2 0x3 0x4 /* pci slot */ 0x9 0xa 0xb 0xc /* usb */ 0x6 0x7 0xe 0x5 /* Audio elgacy SATA */ 0xe0 0xe1 0xe2 0xe3 /* msi */ >; }; timer@41100 { status = "disabled"; }; msi@41600 { msi-available-ranges = <0x80 0x80>; interrupts = < 0xe4 0 0 0 0xe5 0 0 0 0xe6 0 0 0 0xe7 0 0 0>; }; global-utilities@e0000 { status = "disabled"; }; }; pcie@ffe08000 { status = "disabled"; }; pcie@ffe09000 { status = "disabled"; }; };