/* * P3041DS Device Tree Source * * Copyright 2010 - 2015 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /include/ "p3041si-pre.dtsi" / { model = "fsl,P3041DS"; compatible = "fsl,P3041DS"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; aliases{ phy_rgmii_0 = &phy_rgmii_0; phy_rgmii_1 = &phy_rgmii_1; phy_sgmii_1c = &phy_sgmii_1c; phy_sgmii_1d = &phy_sgmii_1d; phy_sgmii_1e = &phy_sgmii_1e; phy_sgmii_1f = &phy_sgmii_1f; phy_xgmii_1 = &phy_xgmii_1; phy_xgmii_2 = &phy_xgmii_2; emi1_rgmii = &hydra_mdio_rgmii; emi1_sgmii = &hydra_mdio_sgmii; emi2_xgmii = &hydra_mdio_xgmii; }; memory { device_type = "memory"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; bman_fbpr: bman-fbpr { size = <0 0x1000000>; alignment = <0 0x1000000>; }; qman_fqd: qman-fqd { size = <0 0x400000>; alignment = <0 0x400000>; }; qman_pfdr: qman-pfdr { size = <0 0x2000000>; alignment = <0 0x2000000>; }; }; dcsr: dcsr@f00000000 { ranges = <0x00000000 0xf 0x00000000 0x01008000>; }; bportals: bman-portals@ff4000000 { ranges = <0x0 0xf 0xf4000000 0x200000>; }; qportals: qman-portals@ff4200000 { ranges = <0x0 0xf 0xf4200000 0x200000>; }; soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; spi@110000 { flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spansion,s25sl12801", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <35000000>; /* input clock */ partition@u-boot { label = "u-boot"; reg = <0x00000000 0x00100000>; read-only; }; partition@kernel { label = "kernel"; reg = <0x00100000 0x00500000>; read-only; }; partition@dtb { label = "dtb"; reg = <0x00600000 0x00100000>; read-only; }; partition@fs { label = "file system"; reg = <0x00700000 0x00900000>; }; }; }; i2c@118100 { eeprom@51 { compatible = "atmel,24c256"; reg = <0x51>; }; eeprom@52 { compatible = "atmel,24c256"; reg = <0x52>; }; }; i2c@119100 { rtc@68 { compatible = "dallas,ds3232"; reg = <0x68>; interrupts = <0x1 0x1 0 0>; }; ina220@40 { compatible = "ti,ina220"; reg = <0x40>; shunt-resistor = <1000>; }; ina220@41 { compatible = "ti,ina220"; reg = <0x41>; shunt-resistor = <1000>; }; ina220@44 { compatible = "ti,ina220"; reg = <0x44>; shunt-resistor = <1000>; }; ina220@45 { compatible = "ti,ina220"; reg = <0x45>; shunt-resistor = <1000>; }; adt7461@4c { compatible = "adi,adt7461"; reg = <0x4c>; }; }; fman@400000{ ethernet@e0000 { phy-handle = <&phy_sgmii_1c>; phy-connection-type = "sgmii"; }; ethernet@e2000 { phy-handle = <&phy_sgmii_1d>; phy-connection-type = "sgmii"; }; ethernet@e4000 { phy-handle = <&phy_sgmii_1e>; phy-connection-type = "sgmii"; }; ethernet@e6000 { phy-handle = <&phy_sgmii_1f>; phy-connection-type = "sgmii"; }; ethernet@e8000 { phy-handle = <&phy_rgmii_1>; phy-connection-type = "rgmii"; }; ethernet@f0000 { phy-handle = <&phy_xgmii_1>; phy-connection-type = "xgmii"; }; hydra_mdio_xgmii: mdio@f1000 { status = "disabled"; phy_xgmii_1: ethernet-phy@4 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <0x4>; }; phy_xgmii_2: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <0x0>; }; }; }; }; rio: rapidio@ffe0c0000 { reg = <0xf 0xfe0c0000 0 0x11000>; port1 { ranges = <0 0 0xc 0x20000000 0 0x10000000>; }; port2 { ranges = <0 0 0xc 0x30000000 0 0x10000000>; }; }; lbc: localbus@ffe124000 { reg = <0xf 0xfe124000 0 0x1000>; ranges = <0 0 0xf 0xe8000000 0x08000000 2 0 0xf 0xffa00000 0x00040000 3 0 0xf 0xffdf0000 0x00008000>; flash@0,0 { compatible = "cfi-flash"; reg = <0 0 0x08000000>; bank-width = <2>; device-width = <2>; }; nand@2,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,elbc-fcm-nand"; reg = <0x2 0x0 0x40000>; partition@0 { label = "NAND U-Boot Image"; reg = <0x0 0x02000000>; read-only; }; partition@2000000 { label = "NAND Root File System"; reg = <0x02000000 0x10000000>; }; partition@12000000 { label = "NAND Compressed RFS Image"; reg = <0x12000000 0x08000000>; }; partition@1a000000 { label = "NAND Linux Kernel Image"; reg = <0x1a000000 0x04000000>; }; partition@1e000000 { label = "NAND DTB Image"; reg = <0x1e000000 0x01000000>; }; partition@1f000000 { label = "NAND Writable User area"; reg = <0x1f000000 0x21000000>; }; }; board-control@3,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis"; reg = <3 0 0x30>; ranges = <0 3 0 0x30>; mdio-mux-emi1 { #address-cells = <1>; #size-cells = <0>; compatible = "mdio-mux-mmioreg", "mdio-mux"; mdio-parent-bus = <&mdio0>; reg = <9 1>; mux-mask = <0x78>; hydra_mdio_rgmii: rgmii-mdio@8 { #address-cells = <1>; #size-cells = <0>; reg = <8>; status = "disabled"; phy_rgmii_0: ethernet-phy@0 { reg = <0x0>; }; phy_rgmii_1: ethernet-phy@1 { reg = <0x1>; }; }; hydra_mdio_sgmii: sgmii-mdio@28 { #address-cells = <1>; #size-cells = <0>; reg = <0x28>; status = "disabled"; phy_sgmii_1c: ethernet-phy@1c { reg = <0x1c>; }; phy_sgmii_1d: ethernet-phy@1d { reg = <0x1d>; }; phy_sgmii_1e: ethernet-phy@1e { reg = <0x1e>; }; phy_sgmii_1f: ethernet-phy@1f { reg = <0x1f>; }; }; }; }; }; pci0: pcie@ffe200000 { reg = <0xf 0xfe200000 0 0x1000>; ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x20000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; pci1: pcie@ffe201000 { reg = <0xf 0xfe201000 0 0x1000>; ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x20000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; pci2: pcie@ffe202000 { reg = <0xf 0xfe202000 0 0x1000>; ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x20000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; pci3: pcie@ffe203000 { reg = <0xf 0xfe203000 0 0x1000>; ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; pcie@0 { ranges = <0x02000000 0 0xe0000000 0x02000000 0 0xe0000000 0 0x20000000 0x01000000 0 0x00000000 0x01000000 0 0x00000000 0 0x00010000>; }; }; }; /include/ "p3041si-post.dtsi"